SN74LS175
Quad D Flip-Flop
The LSTTL / MSI SN74LS175 is a high speed Quad D Flip-Flop.
The device is useful for general flip-flop requirements where clock
and clear inputs are common. The information on the D inputs is
stored during the LOW to HIGH clock transition. Both true and
complemented outputs of each flip-flop are provided. A Master Reset
input resets all flip-flops, independent of the Clock or D inputs, when
LOW.
The LS175 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all ON Semiconductor
TTL families.
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•
•
•
•
•
•
LOW
POWER
SCHOTTKY
Edge-Triggered D-Type Inputs
Buffered-Positive Edge-Triggered Clock
Clock to Output Delays of 30 ns
Asynchronous Common Reset
True and Complement Output
Input Clamp Diodes Limit High Speed Termination Effects
16
1
GUARANTEED OPERATING RANGES
Symbol
V
CC
T
A
I
OH
I
OL
Parameter
Supply Voltage
Operating Ambient
Temperature Range
Output Current – High
Output Current – Low
Min
4.75
0
Typ
5.0
25
Max
5.25
70
– 0.4
8.0
Unit
V
°C
mA
mA
PLASTIC
N SUFFIX
CASE 648
16
1
SOIC
D SUFFIX
CASE 751B
ORDERING INFORMATION
Device
SN74LS175N
SN74LS175D
Package
16 Pin DIP
16 Pin
Shipping
2000 Units/Box
2500/Tape & Reel
©
Semiconductor Components Industries, LLC, 1999
1
December, 1999 – Rev. 6
Publication Order Number:
SN74LS175/D
SN74LS175
CONNECTION DIAGRAM DIP
(TOP VIEW)
V
CC
16
Q
3
15
Q
3
14
D
3
13
D
2
12
Q
2
11
Q
2
10
CP
9
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
1
MR
2
Q
0
3
Q
0
4
D
0
5
D
1
6
Q
1
7
Q
1
8
GND
LOADING
(Note a)
PIN NAMES
D
0
– D
3
CP
MR
Q
0
– Q
3
Q
0
– Q
3
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
True Outputs
Complemented Outputs
HIGH
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
LOW
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40
m
A HIGH/1.6 mA LOW.
LOGIC SYMBOL
4
5
12
13
9
CP
D
0
D
1
D
2
D
3
1
MR
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
3
2
6
7
11
10 14 15
V
CC
= PIN 16
GND = PIN 8
LOGIC DIAGRAM
MR CP D
3
1
9
13
D
2
12
D
1
5
D
0
4
D Q
CP Q
C
D
14
15
D Q
CP Q
C
D
11
10
D Q
CP Q
C
D
6
7
D Q
CP Q
C
D
3
2
Q
3
Q
3
Q
2
Q
2
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
Q
1
Q
1
Q
0
Q
0
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2
SN74LS175
FUNCTIONAL DESCRIPTION
The LS175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q outputs. The Clock and
Master Reset are common. The four flip-flops will store the
state of their individual D inputs on the LOW to HIGH Clock
(CP) transition, causing individual Q and Q outputs to
follow. A LOW input on the Master Reset (MR) will force
all Q outputs LOW and Q outputs HIGH independent of
Clock or Data inputs.
The LS175 is useful for general logic applications where
a common Master Reset and Clock are acceptable.
TRUTH TABLE
Inputs (t = n, MR = H)
D
L
H
Outputs (t = n+1) Note 1
Q
L
H
Q
H
L
Note 1: t = n + 1 indicates conditions after next clock.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
V
IH
V
IL
V
IK
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
2.7
– 0.65
3.5
0.25
V
O
OL
Output LOW Voltage
0.35
I
IH
I
IL
I
OS
I
CC
Input HIGH Current
0.1
Input LOW Current
Short Circuit Current (Note 1)
Power Supply Current
– 20
– 0.4
– 100
18
0.5
20
V
µA
mA
mA
mA
mA
I
OL
= 8.0 mA
0.4
Min
2.0
0.8
– 1.5
Typ
Max
Unit
V
V
V
V
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
V
CC
= MIN, I
IN
= – 18 mA
V
CC
= MIN, I
OH
= MAX, V
IN
= V
IH
or V
IL
per Truth Table
I
OL
= 4.0 mA
V
CC
= V
CC
MIN,
V
IN
= V
IL
or V
IH
per Truth Table
V
CC
= MAX, V
IN
= 2.7 V
V
CC
= MAX, V
IN
= 7.0 V
V
CC
= MAX, V
IN
= 0.4 V
V
CC
= MAX
V
CC
= MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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3
SN74LS175
AC CHARACTERISTICS
(T
A
= 25°C)
Limits
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Maximum Input Clock Frequency
Propagation Delay, MR to Output
Propagation Delay, Clock to Output
Min
30
Typ
40
20
20
13
16
30
30
25
25
Max
Unit
MHz
ns
ns
V
CC
= 5.0 V
C
L
= 15 pF
F
Test Conditions
AC SETUP REQUIREMENTS
(T
A
= 25°C)
Limits
Symbol
t
W
t
s
t
h
t
rec
Parameter
Clock or MR Pulse Width
Data Setup Time
Data Hold Time
Recovery Time
Min
20
20
5.0
25
Typ
Max
Unit
ns
ns
ns
ns
V
CC
= 5 0 V
5.0
Test Conditions
AC WAVEFORMS
1/f
max
CP
1.3 V
t
s(H)
D
*
1.3 V
t
h(H)
t
s(L)
t
w
1.3 V
t
h(L)
1.3 V
t
PHL
1.3 V
t
PLH
1.3 V
Q
CP
Q
t
PLH
1.3 V
1.3 V
t
PHL
1.3 V
1.3 V
MR
1.3 V
t
W
1.3 V
t
rec
1.3 V
1.3 V
t
PLH
1.3 V
t
PHL
1.3 V
Q
Q
*The shaded areas indicate when the input is permitted to
*change
for predictable output performance.
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
DEFINITIONS OF TERMS
SETUP TIME (t
s
) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
RECOVERY TIME (t
rec
) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW to HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
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4
SN74LS175
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0
_
10
_
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0
_
10
_
0.51
1.01
B
1
8
F
S
C
L
–T–
H
G
D
16 PL
SEATING
PLANE
K
J
T A
M
M
0.25 (0.010)
M
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5
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