PCI Express™ Jitter Attenuator
ICS874003-05
DATASHEET
General Description
The ICS874003-05 is a high performance Differential-to-LVDS Jitter
Attenuator designed for use in PCI Express systems. In some PCI
Express systems, such as those found in desktop PCs, the PCI
Express clocks are generated from a low bandwidth, high phase
noise PLL frequency synthesizer. In these systems, a jitter
attenuator may be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer and from
the system board. The ICS874003-05 has a bandwidth of 6.2MHz
with <1dB peaking, easily meeting PCI Express Gen2 PLL
requirements.
The ICS874003-05 uses IDT’s 3 Generation FemtoClock™ PLL
technology to achieve the lowest possible phase noise. The device is
packaged in a 20-Lead TSSOP package, making it ideal for use in
space constrained applications such as PCI Express add-in cards.
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Features
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Three differential LVDS output pairs
One differential clock input
CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, HCSL, SSTL
Input frequency range: 98MHz to 128MHz
Output frequency range: 98MHz to 320MHz
VCO range: 490MHz - 640MHz
Supports PCI-Express Spread-Spectrum Clocking
High PLL bandwidth allows for better input tracking
PCI Express (2.5 Gb/s) and Gen 2 (5 Gb/S) jitter compliant
0°C to 70°C ambient operating temperature
Full 3.3V operating supply
Available in lead-free (RoHS 6) packages
F_SEL[2:0] Function Table
Inputs
F_SEL2
0
(default)
1
0
1
0
1
0
1
F_SEL1
0
(default)
0
1
1
0
0
1
1
F_SEL0
0
(default)
0
0
0
1
1
1
1
Outputs
QA[0:1],
nQA[0:1]
÷2
÷5
÷4
÷2
÷2
÷5
÷4
÷4
QB0, nQB0
÷2
÷2
÷2
÷4
÷5
÷4
÷5
÷4
Pin Assignment
QA1
V
DDO
QA0
nQA0
MR
F_SEL0
nc
V
DDA
F_SEL1
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nQA1
V
DDO
QB0
nQB0
F_SEL2
OEB
GND
nCLK
CLK
OEA
ICS874003-05
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm package body
G Package
Top View
ICS874003BG-05 REVISION B MARCH 21, 2014
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©2014 Integrated Device Technology, Inc.
ICS874003-05 Data Sheet
PCI EXPRESS™
JITTER ATTENUATOR
Block Diagram
OEA
Pullup
F_SEL2:0 Pulldown
3
QA0
÷5
÷4
÷2
(default)
CLK Pulldown
nQA0
QA1
nCLK Pullup
Phase
Detector
VCO
490 - 640MHz
3
nQA1
M = ÷5
(fixed)
÷5
÷4
÷2
(default)
QB0
nQB0
MR Pulldown
OEB
Pullup
ICS874003BG-05 REVISION B MARCH 21, 2014
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©2014 Integrated Device Technology, Inc.
ICS874003-05 Data Sheet
PCI EXPRESS™
JITTER ATTENUATOR
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1, 20
2, 19
3, 4
Name
QA1, nQA1
V
DDO
QA0, nQA0
Output
Power
Output
Type
Description
Bank A differential output pair. LVDS interface levels.
Output supply pins.
Bank A differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs (nQx) to go low and the inverted outputs (Qx) to go
high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
Frequency select pin for QAx/nQAx and QB0/nQB0 outputs.
LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Core supply pin.
Pullup
Pulldown
Pullup
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
active. When LOW, the QAx/nQAx outputs are in a high-impedance state.
LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Power supply ground.
Pullup
Output enable pin for QB0 pins. When HIGH, the QB0/nQB0 outputs are
active. When LOW, the QB0/nQB0 outputs are in a high-impedance state.
LVCMOS/LVTTL interface levels.
Bank B differential output pair. LVDS interface levels.
5
MR
Input
Pulldown
6,
9,
16
7
8
10
11
12
13
14
15
17, 18
F_SEL0,
F_SEL1,
F_SEL2
nc
V
DDA
V
DD
OEA
CLK
nCLK
GND
OEB
nQB0, QB0
Input
Unused
Power
Power
Input
Input
Input
Power
Input
Output
Pulldown
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Table 3. Output Enable Function Table
Inputs
OEA
0
1 (default)
OEB
0
1 (default)
Outputs
QA[0:1], nQA[0:1]
High Impedance
Enabled
QB0, nQB0
High Impedance
Enabled
ICS874003BG-05 REVISION B MARCH 21, 2014
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©2014 Integrated Device Technology, Inc.
ICS874003-05 Data Sheet
PCI EXPRESS™
JITTER ATTENUATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVDS)
Continuos Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
86.7°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Positive Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.16
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
75
16
75
Units
V
V
V
mA
mA
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
OEA, OEB
Input High
Current
F_SEL0, F_SEL1,
F_SEL2, MR
OEA, OEB
I
IL
Input Low
Current
F_SEL0, F_SEL1,
F_SEL2, MR
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
ICS874003BG-05 REVISION B MARCH 21, 2014
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©2014 Integrated Device Technology, Inc.
ICS874003-05 Data Sheet
PCI EXPRESS™
JITTER ATTENUATOR
Table 4C. Differential DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
I
IH
Parameter
Input High
Current
Input Low
Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
I
IL
V
PP
V
CMR
Peak-to-Peak Voltage;
NOTE 1
Common Mode Input
Voltage; NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Table 4D. LVDS DC Characteristics,
V
DD
= V
DDO
= = 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.20
1.35
Test Conditions
Minimum
275
Typical
375
Maximum
485
50
1.50
50
Units
mV
mV
V
mV
ICS874003BG-05 REVISION B MARCH 21, 2014
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©2014 Integrated Device Technology, Inc.
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