NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
March 1999
NM25C040
4K-Bit Serial CMOS EEPROM
(Serial Peripheral Interface (SPI) Synchronous Bus)
General Description
The NM25C040 is a 4096-bit CMOS EEPROM with an SPI
compatible serial interface. The NM25C040 is designed for data
storage in applications requiring both non-volatile memory and in-
system data updates. This EEPROM is well suited for applications
using the 68HC11 series of microcontrollers that support the SPI
interface for high speed communication with peripheral devices
via a serial bus to reduce pin count. The NM25C040 is imple-
mented in Fairchild Semiconductor’s floating gate CMOS process
that provides superior endurance and data retention.
The serial data transmission of this device requires four signal
lines to control the device operation: Chip Select (CS), Clock
(SCK), Data In (SI), and Serial Data Out (SO). All programming
cycles are completely self-timed and do not require an erase
before WRITE.
BLOCK WRITE protection is provided by programming the STA-
TUS REGISTER with one of four levels of write protection.
Additionally, separate WRITE enable and WRITE disable instruc-
tions are provided for data protection.
Hardware data protection is provided by the WP pin to protect
against inadvertent programming. The HOLD pin allows the serial
communication to be suspended without resetting the serial
sequence.
Features
s
2.1 MHz clock rate @ 2.7V to 5.5V
s
4096 bits organized as 512 x 8
s
Multiple chips on the same 3-wire bus with separate chip
select lines
s
Self-timed programming cycle
s
Simultaneous programming of 1 to 4 bytes at a time
s
Status register can be polled during programming to monitor
READY/BUSY
s
Write Protect (WP) pin and write disable instruction for both
hardware and software write protection
s
Block write protect feature to protect against accidental
writes
s
Endurance: 1,000,000 data changes
s
Data retention greater than 40 years
s
Packages available: 8-pin DIP, 8-pin SO, or 8-pin TSSOP
Block Diagram
CS
HOLD
SCK
SI
Instruction
Register
Instruction
Decoder
Control Logic
and Clock
Generators
V
CC
V
SS
WP
Address
Counter/
Register
Program
Enable
V
PP
EEPROM Array
4096 Bits
(512 x 8)
High Voltage
Generator
and
Program
Timer
Decoder
1 of 512
Read/Write Amps
Data In/Out Register
8 Bits
Data Out
Buffer
SO
Non-Volatile
Status Register
DS012401-1
© 1999 Fairchild Semiconductor Corporation
NM25C040 Rev. D.1
1
www.fairchildsemi.com
NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Connection Diagram
Dual-In-Line Package (N), SO Package (M8),
and TSSOP Package (MT8)
CS
SO
WP
V
SS
1
2
NM25C040
3
4
6
5
SCK
SI
DS012401-2
8
7
V
CC
HOLD
Top View
See Package Number N08E (N), M08A (M8), and MTC08 (MT8)
Pin Names
CS
SO
WP
V
SS
SI
SCK
HOLD
V
CC
Chip Select Input
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock Input
Suspends Serial Data
Power Supply
Ordering Information
NM
25
C
XX
LZ E
XX
Package
Letter
N
M8
MT8
None
V
E
Blank
L
LZ
040
C
W
Interface
25
NM
Description
8-pin DIP
8-pin SO
8-pin TSSOP
0 to 70°C
-40 to +125°C
-40 to +85°C
4.5V to 5.5V
2.7V to 4.5V
2.7V to 4.5V and
<1µA Standby Current
4K, mode 0
CMOS technology
Total Array write protect
SPI
Fairchild Nonvolatile
Memory Prefix
Temp. Range
Voltage Operating Range
Density/Mode
2
NM25C040 Rev. D.1
www.fairchildsemi.com
NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Standard Voltage 4.5
≤
V
CC
≤
5.5V Specifications
Operating Conditions
Absolute Maximum Ratings
(Note 1)
Ambient Storage Temperature
All Input or Output Voltage with
Respect to Ground
Lead Temp. (Soldering, 10 sec.)
ESD Rating
-65°C to +150°C
+6.5V to -0.3V
+300°C
2000V
Ambient Operating Temperature
NM25C040
NM25C040E
NM25C040V
Power Supply (V
CC
)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
4.5V to 5.5V
DC and AC Electrical Characteristics
4.5V
≤
V
CC
≤
5.5V (unless otherwise specified)
Symbol
I
CC
I
CCSB
I
IL
I
OL
V
IL
V
IH
V
OL
V
OH
f
OP
t
RI
t
FI
t
CLH
t
CLL
t
CSH
t
CSS
t
DIS
t
HDS
t
CSN
t
DIN
t
HDN
t
PD
t
DH
t
LZ
t
DF
t
HZ
t
WP
Parameter
Operating Current
Standby Current
Input Leakage
Output Leakage
CMOS Input Low Voltage
CMOS Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
Input Rise Time
Input Fall Time
Clock High Time
Clock Low Time
Min CS High Time
CS Setup Time
Data Setup Time
HOLD Setup Time
CS Hold Time
Data Hold Time
HOLD Hold Time
Output Delay
Output Hold Time
HOLD to Output Low Z
Output Disable Time
HOLD to Output High Z
Write Cycle Time
Conditions
CS = V
IL
CS = V
CC
V
IN
= 0 to V
CC
V
OUT
= GND to V
CC
Min
Max
3
50
Units
mA
µA
µA
µA
V
V
V
V
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
-1
-1
-0.3
0.7 * V
CC
+1
+1
V
CC
* 0.3
V
CC
+ 0.3
0.4
I
OL
= 1.6 mA
I
OH
= -0.8 mA
V
CC
- 0.8
2.1
2.0
2.0
(Note 2)
(Note 2)
(Note 3)
190
190
240
240
100
90
240
100
90
C
L
= 200 pF
0
100
C
L
= 200 pF
1–4 Bytes
240
100
10
240
ns
ns
ns
ns
ns
ms
Capacitance
T
A
= 25°C, f = 2.1/1 MHz (Note 4)
Symbol
C
OUT
C
IN
AC Test Conditions
Output Load
Input Pulse Levels
Timing Measurement Reference Level
C
L
= 200 pF
0.1 * V
CC
– 0.9 * V
CC
0.3 * V
CC
- .07 * V
CC
Test
Output Capacitance
Input Capacitance
Typ Max Units
3
2
8
6
pF
pF
Note 1:
Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2:
The f
OP
frequency specification specifies a minimum clock period of 1/f
OP
. Therefore, for every f
OP
clock cycle, t
CLH
+ t
CLL
must be equal to or greater than 1/f
OP
. For
example, if the 2.1MHz period = 476ns and t
CLH
= 190ns, t
CLL
must be 286ns.
Note 3:
CS must be brought high for a minimum of t
CSH
between consecutive instruction cycles.
Note 4:
This parameter is periodically sampled and not 100% tested.
3
NM25C040 Rev. D.1
www.fairchildsemi.com
NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
Low Voltage 2.7V
≤
V
CC
≤
4.5V Specifications
Operating Conditions
Absolute Maximum Ratings
(Note 5)
Ambient Storage Temperature
All Input or Output Voltage with
Respect to Ground
Lead Temp. (Soldering, 10 sec.)
ESD Rating
-65°C to +150°C
+6.5V to -0.3V
+300°C
2000V
Ambient Operating Temperature
NM25C040L/LZ
NM25C040LE/LZE
NM25C040LV
Power Supply (V
CC
)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
2.7V–4.5V
DC and AC Electrical Characteristics
2.7V
≤
V
CC
≤
4.5V (unless otherwise specified)
25C040L/LE
25C040LZ/ZE
Symbol
I
CC
I
CCSB
I
IL
I
OL
V
IL
V
IH
V
OL
V
OH
f
OP
t
RI
t
FI
t
CLH
t
CLL
t
CSH
t
CSS
t
DIS
t
HDS
t
CSN
t
DIN
t
HDN
t
PD
t
DH
t
LZ
t
DF
t
HZ
t
WP
25C040LV
Min
Max
3
10
N/A
-1
-1
-0.3
V
CC
* 0.7
V
CC
- 0.8
1
1
V
CC
* 0.3
V
CC
+ 0.3
0.4
1.0
2.0
2.0
410
410
500
500
100
240
500
100
240
Parameter
Operating Current
Standby Current
Input Leakage
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
SCK Frequency
Input Rise Time
Input Fall Time
Clock High Time
Clock Low Time
Min. CS High Time
CS Setup Time
Data Setup Time
HOLD Setup Time
CS Hold Time
Data Hold Time
HOLD Hold Time
Output Delay
Output Hold Time
HOLD Output Low Z
Output Disable Time
HOLD to Output Hi Z
Write Cycle Time
Part
L
LZ
Conditions
CS = V
IL
CS = V
CC
V
IN
= 0 to V
CC
V
OUT
= GND to V
CC
Min.
Max.
3
10
1
Units
mA
µA
µA
µA
µA
V
V
V
V
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
-1
-1
-0.3
V
CC
* 0.7
1
1
V
CC
* 0.3
V
CC
+ 0.3
0.4
I
OL
= 0.8 mA
I
OH
= –0.8 mA
V
CC
- 0.8
1.0
2.0
2.0
(Note 6)
(Note 6)
(Note 7)
410
410
500
500
100
240
500
100
240
C
L
= 200 pF
0
240
C
L
= 200 pF
1-4 Bytes
500
240
15
500
0
500
240
500
240
15
ns
ns
ns
ns
ns
ms
Capacitance
T
A
= 25°C, f = 2.1/1 MHz (Note 8)
Symbol
C
OUT
C
IN
AC Test Conditions
Output Load
Input Pulse Levels
Timing Measurement Reference Level
C
L
= 200pF
0.1 * V
CC
- 0.9 * V
CC
0.3 * V
CC
- 0.7 * V
CC
Test
Output Capacitance
Input Capacitance
Typ Max Units
3
2
8
6
pF
pF
Note 5:
Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Note 6:
The f
OP
frequency specification specifies a minimum clock period of 1/f
OP
. Therefore, for every f
OP
clock cycle, t
CLH
+ t
CLL
must be equal to or greater than 1/f
OP
. For example,
if the 2.1MHz period = 476ns and t
CLH
= 190ns, t
CLL
must be 286ns.
Note 7:
CS must be brought high for a minimum of t
CSH
between consecutive instruction cycles.
Note 8:
This parameter is periodically sampled and not 100% tested.
4
NM25C040 Rev. D.1
www.fairchildsemi.com
NM25C040 4K-Bit Serial CMOS EEPROM
(Serial Periphrial Interface (SPI) Synchronous Bus)
AC Test Conditions
(Continued)
VIH
CS
VIL
VIH
SCK
VIL
VIH
SI
VIL
VOH
SO
VOL
FIGURE 1. Synchronous Data Timing Diagram
FIGURE 2. HOLD Timing
,,
,
tCSS
tCLH
tCLL
tDIS
tPD
SCK
tCSH
tCSN
tDIN
tDH
tDF
DS012401-3
tHDS
HOLD
tHDN
tHDS
tHDN
tHZ
SO
tLZ
DS012401-6
FIGURE 3. SPI Serial Interface
MASTER MCU
DATA OUT (MOSI)
DATA IN (MISO)
SERIAL CLOCK (CLK)
NM25C040
SPI
CHIP
SELECTION
SS0
SS1
SS2
SS3
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
DS012401-4
5
NM25C040 Rev. D.1
www.fairchildsemi.com
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