THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
APRIL 1995
15HSC Series
ADVANCE INFORMATION
DS3593-2.3
15HSC Series
RADIATION HARD HIGH SPEED CMOS/SOS LOGIC
The 15HSC Series offer the conbined benefits of low power,
high speed CMOS with the inherent latch up immunity, Single
Event Upset (SEU) immunity and high level of radiation
hardness of Silicon on Sapphire technology.
The 15HSC Series of CMOS/SOS devices are pin
compatible with the 54LS Series and the 54HSC Series, but
with a higher speed capability.
Further device types to those listed will be available shortly.
Please contact GPS for further information.
DEVICE TYPES
15HSC138
15HSC163
3-Line to 8-Line Decoder/Multiplexer
Synchronous 4-Bit Counter
FEATURES
s
Radiation Hard to 1.5µm CMOS/SOS Technology
s
High SEU Immunity
s
Latch Up Free
s
Low Power CMOS/SOS Technology
s
Plug In Replacement for 54/74LS, HC and HCT
s
Dual In Line or Flatpack Packages
s
High Speed (Toggle Rate 100MHz)
1
15HSC Series
DC CHARACTERISTICS AND RATINGS
Parameter
Supply Voltage
Input Voltage
Current Through Any Pin
Operating Temperature
Storage Temperature
Min
-0.5
-0.3
-25
-55
-65
Max
10
V
DD
+0.3
+25
125
150
Units
V
V
mA
°C
°C
Note:
Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these conditions, or at
any other condition above those indicated in the operations
section of this specification, is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
Figure 1: Absolute Maximum Ratings
Total dose radiation not
exceeding 3x10
5
Rad(Si)
Symbol
V
DD
V
IH1
V
IL1
V
IH2
V
IL2
V
OH
Parameter
Supply Voltage
HST Input High Voltage
HST Input Low Voltage
HSC Input High Voltage
HSC Input Low Voltage
Output High Voltage
Conditions
-
-
-
-
-
V
IN
= V
IH
or V
IL
I
OH
= -20µA*
I
OH
= -6.0mA*
I
OH
= -11.0mA
V
OL
Output Low Voltage
V
IN
= V
IH
or V
IL
I
OL
= 20µA*
I
OL
= 6.0mA*
I
OL
= 9.0mA
I
IL
I
OL
I
DD
Input Leakage Current
Output Leakage Current
Quiescent Current
V
IN
= V
DD
or V
SS
All inputs
V
OUT
= V
DD
or V
SS
Outputs disabled
V
IN
= V
DD
Outputs unloaded
V
DD
= 5V±10%, over full operating temperature range.
* = Guaranteed but not tested.
-
-
1
mA
-
-
50
µA
-
-
-
-
-
-
-
-
0.1
0.2
0.4
±10
V
V
V
µA
V
DD
-0.1
3.7
2.5
-
-
-
-
-
-
V
V
V
Min
4.5
2.0
-
3.5
-
Typ
5.0
-
-
-
-
Max
5.5
-
0.8
-
1.5
Units
V
V
V
V
V
Figure 2: Electrical Characteristics
2
15HSC Series
15HSC138 : 3-Line to 8-Line Decoder/Multiplexer
Enable Inputs
G
1
X
X
L
H
H
H
H
H
H
H
H
GN
2A
GN
2B
H
X
X
L
L
L
L
L
L
L
L
X
H
X
L
L
L
L
L
L
L
L
Select Inputs
C
X
X
X
L
L
L
L
H
H
H
H
B
X
X
X
L
L
H
H
L
L
H
H
A
X
X
X
L
H
L
H
L
H
L
H
Y
0
H
H
H
L
H
H
H
H
H
H
H
Y
1
H
H
H
H
L
H
H
H
H
H
H
Y
2
H
H
H
H
H
L
H
H
H
H
H
Outputs
Y
3
H
H
H
H
H
H
L
H
H
H
H
Y
4
H
H
H
H
H
H
H
L
H
H
H
Y
5
H
H
H
H
H
H
H
H
L
H
H
Y
6
H
H
H
H
H
H
H
H
H
L
H
Y
7
H
H
H
H
H
H
H
H
H
H
L
H = high level, L = low level, X = irrelevant
Figure 3: Function Table
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Propagation delay. Address to Output
Propagation delay. Address to Output.
Propagation delay. G to Output
Propagation delay. G to Output
Spice
Simulation
7.6
7.4
9.3
8.8
Max.
15
15
15
15
Units
ns
ns
ns
ns
Figure 4: Switching Characteristics
A
B
C
GN2A
GN2B
G1
Y7
VSS
1
2
3
4
5
6
7
8
Top
View
16 VCC
15 Y0
14 Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
VCC 16
Y0 15
Y1 14
Y2 13
Y3 12
Y4 11
Y5 10
Y6
9
Bottom
View
1 A
2 B
3 C
4 GN2A
5 GN2B
6 G1
7 Y7
8 VSS
Figure 5: DIL Pin Out
Figure 6: Flatpack Pin Out
3
15HSC Series
15HSC163 : 4-Bit Counter with Synchronous Clear
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Parameter
Propagation delay. Clock to RCO
Propagation delay. Clock to RCO
Propagation delay. Clock to any Q
Propagation delay. Clock to any Q
Propagation delay. ENT to RCO
Propagation delay. ENT to RCO
Spice
Simulation
11.5
11.4
9.4
9.6
8.5
8.4
Max.
15
15
15
15
15
15
Units
ns
ns
ns
ns
ns
ns
Figure 7: Switching Characteristics
CLRN
CLK
A
B
C
D
ENP
GND
1
2
3
4
5
6
7
8
Top
View
16 VDD
15 RCO
14 QA
13 QB
12 QC
11 QD
10 ENT
9 LOADN
VDD 16
RCO 15
QA 14
QB 13
QC 12
QD 11
ENT 10
LOADN
9
Bottom
View
1 CLRN
2 CLK
3 A
4 B
5 C
6 D
7 ENP
8 GND
Figure 8: DIL Pin Out
Figure 9: Flatpack Pin Out
4
FPGA/CPLD
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