SHARC+ Dual Core
DSP with ARM Cortex-A5
Preliminary Technical Data
SYSTEM FEATURES
Dual enhanced SHARC+ high performance floating-point
cores
Up to 450 MHz per SHARC+ core
Up to 5 Mbits (640 kB) L1SRAM memory per core with
parity (optional ability to configure as cache)
32-bit, 40-bit, and 64-bit floating-point support
32-bit fixed point
Byte, short-word, word, long-word addressed
ARM Cortex-A5 core
450 MHz/720 DMIPS with Neon/VFPv4-D16/Jazelle
32 kB L1 instruction cache/32 kB L1 data cache
256 kB L2 cache with parity
Powerful DMA system
On-chip memory protection
Integrated safety features
ADSP-SC582/583/584/587/589/ADSP-21583/584/587
19 mm × 19 mm 349/529 BGA (0.8 pitch), RoHS compliant
Low system power across automotive temperature range
MEMORY
Large on-chip L2 SRAM with ECC protection, up to 256 kB
On-chip L2 ROM (512 kB)
Two L3 interfaces optimized for low system power, providing
16-bit interface to DDR3, DDR2 or LPDDR1 SDRAM devices
ADDITIONAL FEATURES
Security and Protection
Crypto hardware accelerators
Fast secure boot with IP protection
Support for TrustZone
®
Accelerators
High performance pipelined FFT/IFFT engine
FIR, IIR, HAE, SINC offload engines
SYSTEM CONTROL
SECURITY AND PROTECTION
SYSTEM PROTECTION (SPU)
SYSTEM MEMORY
PROTECTION UNIT (SMPU)
FAULT MANAGEMENT
ARM® TrustZone® SECURITY
DUAL CRC
WATCHDOGS
OTP MEMORY
THERMAL SENSOR
PROGRAM FLOW
SYS EVENT CONTROLLER (SEC)
TRIGGER ROUTING (TRU)
SYSTEM CROSSBAR AND DMA SUBSYSTEM
CLOCK, RESET, AND POWER
CLOCK GENERATION (CGU)
CLOCK DISTRIBUTION
UNIT (CDU)
REAL TIME CLOCK (RTC)
RESET CONTROL (RCU)
POWER MANAGEMENT (DPM)
DEBUG UNIT
ARM® CoreSight
TM
WATCHPOINTS (SWU)
16
DATA
16
DATA
L1 CACHE
32 kB L1 I-CACHE
32 kB L1 D-CACHE
L2 CACHE
256 kB (PARITY)
CORE 0
CORE 1
CORE 2
PERIPHERALS
SRU
4× PRECISION CLOCK
GENERATORS
ASRC
8× PAIRS
2x DAI
FULL SPORT 2x PIN
0-7
BUFFER
S
L1 SRAM (PARITY)
5M BITS (640 kB)
SRAM/CACHE
S
L1 SRAM (PARITY)
5M BITS (640 kB)
SRAM/CACHE
2× S/PDIF Rx/Tx
3× I
2
C
2× LINK PORTS
2× SPI + 1× QUAD SPI
3× UARTs
1× EPPI
3× ePWM
8× TIMERS + 1× COUNTER
ADC CONTROL MODULE
(ACM)
ASYNC MEMORY (16-BIT)
2× CAN2.0
G
P
I
O
L3 MEMORY
INTERFACES
DDR3
DDR2
LPDDR1
DDR3
DDR2
LPDDR1
SYSTEM
L2 MEMORY
2M BITS (256 kB)
L2 SRAM (ECC)
4M BITS (512 kB)
2 × 2M BITS ROM
SYSTEM
ACCELERATION
DSP FUNCTIONS
(FFT/iFFT, FIR, IIR, HAE/SINC)
ENCRYPTION/DECRYPTION
SD/SDIO/eMMC
MLB 3-PIN
2× EMAC
SINC FILTER
8x SHARC FLAGS
2× USB 2.0 HS
MLB 6-PIN
PCIe2.0 (1 lane)
HADC (8 CHAN, 12-BIT)
Figure 1. Processor Block Diagram
Rev. PrF
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Technical Support
www.analog.com
ADSP-SC582/583/584/587/589/ADSP-21583/584/587
TABLE OF CONTENTS
General Description ................................................. 3
ARM Cortex-A5 Processor ...................................... 5
SHARC Processor ................................................. 6
SHARC+ Core Architecture .................................... 8
System Infrastructure ........................................... 10
System Memory Map ........................................... 11
Security Features ................................................ 14
Safety Features ................................................... 14
Processor Peripherals ........................................... 15
System Acceleration ............................................ 20
System Design .................................................... 20
System Debug .................................................... 23
Development Tools ............................................. 23
Additional Information ........................................ 24
Related Signal Chains .......................................... 24
Security Features Disclaimer .................................. 24
ADSP-SC58x/ADSP-2158x Detailed Signal
Descriptions ...................................................... 25
349-Ball CSP_BGA Signal Descriptions ....................... 30
GPIO Multiplexing for 349-Ball CSP_BGA .................. 39
529-Ball CSP_BGA Signal Descriptions ....................... 42
Preliminary Technical Data
GPIO Multiplexing for 529-Ball CSP_BGA ................... 54
ADSP-SC58x/ADSP-2158x Designer Quick Reference .... 58
Specifications ........................................................ 80
Operating Conditions ........................................... 80
Electrical Characteristics ....................................... 83
Absolute Maximum Ratings ................................... 87
ESD Sensitivity ................................................... 87
Package Information ............................................ 87
Timing Specifications ........................................... 88
Environmental Conditions .................................. 152
ADSP-SC58x/ADSP-2158x 349-Ball BGA Ball
Assignments .................................................... 153
Numerical by Ball Number ................................... 153
Alphabetical by Pin Name .................................... 155
ADSP-SC58x/ADSP-2158x 529-Ball BGA Ball
Assignments .................................................... 158
Numerical by Ball Number ................................... 158
Alphabetical by Pin Name .................................... 161
Outline Dimensions .............................................. 165
Surface-Mount Design ........................................ 166
Pre Release Products .......................................... 167
REVISION HISTORY
2/16—Revision PrE to Revision PrF
Revised
Processor Comparison ................................... 4
Revised
Processor Comparison for Automotive ............... 4
Updated
Dynamic Memory Controller (DMC) ............. 15
Updated
Digital Audio Interface (DAI) ....................... 15
Updated
Serial Ports (SPORT) .................................. 15
Updated
Precision Clock Generators (PCG) ................. 16
Changed Max specification for f
SPICLKPROG
parameter in
Clock Related Operating Conditions ........................... 81
Rev. PrF
|
Page 2 of 168 |
February 2016
Preliminary Technical Data
ADSP-SC582/583/584/587/589/ADSP-21583/584/587
Table 1. Common Product Features
DAI (includes SRU)
Full SPORTs
S/PDIF Rx/Tx
ASRCs
Precision Clock Generators
2
I C (TWI)
Quad Data Bit SPI
Dual Data Bit SPI
CAN2.0
UARTs
Link Ports
Enhanced PPI
GP Timer
1
GP Counter
Enhanced PWMs
2
Watchdog Timers
ADC Control Module
Static Memory Controller
Hardware Accelerators
High Performance FFT/IFFT
FIR/IIR
Harmonic Analysis Engine
SINC Filter
Security Crypto Engine
Multi-channel 12-bit ADC
1
GENERAL DESCRIPTION
The ADSP-SC58x/ADSP-2158x processors are members of the
SHARC
®
family of products. The ADSP-SC58x processor is
based on the SHARC+ dual-core and the ARM Cortex-A5 core.
The ADSP-SC58x/ADSP-2158x SHARC processors are mem-
bers of the SIMD SHARC family of DSPs that feature Analog
Devices Super Harvard Architecture. These 32-bit/40-bit/64-bit
floating-point processors are optimized for high performance
audio/floating-point applications with their large on-chip
SRAM, multiple internal buses to eliminate I/O bottlenecks, and
innovative digital audio interfaces (DAI). New enhancements to
the SHARC+ core add cache enhancements, branch prediction,
and other instruction set improvements—all while maintaining
instruction set compatibility to previous SHARC products.
By integrating a rich set of industry-leading system peripherals
and memory (see
Table 1, Table 2,
and
Table 3),
the
ARM/SHARC processor is the platform of choice for next-gen-
eration applications that require RISC-like programmability,
multimedia support, and leading-edge signal processing in one
integrated package. These applications span a wide array of
markets, from automotive and pro-audio to industrial-based
applications that require high floating-point performance.
Table 2
provides feature comparison information for features
that vary across the standard processors.
Table 3
provides feature comparison information for features
that vary across the automotive processors.
ADSP-SC58x / ADSP-2158x
2
2
×
4
2
×
1
2
×
4
2
×
2
3
1
2
2
3
2
1
8
1
3
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
8-ch
Eight timers are available in the 529-BGA package only. The 349-BGA package
does not include Timer 6 and 7.
2
Three ePWMs are available in the 529-BGA package only. The 349-BGA package
does not include PWM 2.
Rev. PrF
|
Page 3 of 168 |
February 2016
ADSP-SC582/583/584/587/589/ADSP-21583/584/587
Table 2. Processor Comparison
Processor Feature
ARM Cortex-A5 (MHz max)
ARM Core L1 Cache (I, D kB)
ARM Core L2 Cache (kB)
SHARC+ Core1 (MHz max)
SHARC+ Core2 (MHz max)
SHARC L1 SRAM/core (kB)
L2 SRAM (shared) (kB)
L2 ROM (shared) (kB)
DDR3/DDR2/LPDDR1
Controller (16-bit)
USB 2.0 HS + PHY (host/device/OTG)
USB 2.0 HS + PHY (host/device)
10/100 Std EMAC
10/100/1000 Std/AVB EMAC + Timer
IEEE-1588
SDIO/eMMC
PCIe 2.0 (1 Lane)
Real Time Clock (RTC)
GPIO + DAI Pins
Package Options: 19 mm × 19 mm
ADSP-
SC582
450
32, 32
256
450
–
640
256
512
1
1
–
–
1
–
–
–
80 + 28
349-BGA
ADSP-
SC583
450
32, 32
256
450
450
384
256
512
1
1
–
–
1
–
–
–
80 + 28
349-BGA
ADSP-
SC584
450
32, 32
256
450
450
640
256
512
1
1
–
–
1
–
–
–
80 + 28
349-BGA
ADSP-
SC587
450
32, 32
256
450
450
640
256
512
2
1
1
1
1
1
–
1
102 + 40
529-BGA
ADSP-
SC589
450
32, 32
256
450
450
640
256
512
2
1
1
1
1
Preliminary Technical Data
System
Memory
ADSP-
21583
–
–
–
450
450
384
256
512
1
–
–
–
–
–
–
–
80 + 28
349-BGA
ADSP-
21584
–
–
–
450
450
640
256
512
1
–
–
–
–
–
–
–
80 + 28
349-BGA
ADSP-
21587
–
–
–
450
450
640
256
512
2
–
–
–
–
–
–
1
102 + 40
529-BGA
1
1
1
102 + 40
529-BGA
Table 3. Processor Comparison for Automotive
Processor Feature
ADSP-SC583W ADSP-SC584W ADSP-SC587W ADSP-SC589W ADSP-21583W ADSP-21584W
ARM Cortex-A5 (MHz max)
450
450
450
450
–
–
ARM Core L1 Cache (I, D kB)
32, 32
32, 32
32, 32
32, 32
–
–
ARM Core L2 Cache (kB)
256
256
256
256
–
–
SHARC+ Core1 (MHz max)
450
450
450
450
450
450
SHARC+ Core2 (MHz max)
450
450
450
450
450
450
SHARC L1 SRAM/core (kB)
384
640
640
640
384
640
L2 SRAM (shared) (kB)
256
256
256
256
256
256
L2 ROM (shared) (kB)
512
512
512
512
512
512
DDR3/DDR2/LPDDR1
1
1
2
2
1
1
Controller (16-bit)
USB 2.0 HS + PHY (host/device/OTG)
1
1
1
1
–
–
USB 2.0 HS + PHY (host/device)
–
–
1
1
–
–
10/100 Std EMAC
–
–
1
1
–
–
10/100/1000 Std/AVB EMAC + Timer
1
1
1
1
–
–
IEEE-1588
SDIO/eMMC
–
–
1
1
–
–
PCIe 2.0 (1 Lane)
–
–
–
1
–
–
MLB 3-pin/6-pin
1
1
1
1
1
1
Real Time Clock (RTC)
–
–
1
1
–
–
GPIO + DAI Pins
80 + 28
80 + 28
102 + 40
102 + 40
80 + 28
80 + 28
Package Options: 19 mm × 19 mm
349-BGA
349-BGA
529-BGA
529-BGA
349-BGA
349-BGA
System
Memory
Rev. PrF
|
Page 4 of 168 |
February 2016
Preliminary Technical Data
ARM CORTEX-A5 PROCESSOR
ADSP-SC582/583/584/587/589/ADSP-21583/584/587
• ARM v7 debug architecture
• Trace support through an embedded trace macrocell
(ETM) interface
• Extension: vector floating-point unit (IEEE754) with trap-
less execution
• Extension: media processing engine (MPE) with NEON
technology
• Extension: Jazelle hardware acceleration
The ARM Cortex-A5 processor (Figure
2)
is a high performance
processor with the following features:
• Instruction and Data L1 cache units (32/32K bytes)
• In-order pipeline with dynamic branch prediction
• ARM, Thumb, and ThumbEE instruction set support
• TrustZone security extensions
• Harvard level 1 memory system with a memory manage-
ment unit (MMU)
EMBEDDED TRACE MACROCELL
(ETM) INTERFACE
CoreSight INTERFACE
DEBUG
CP15
NEON MEDIA
PROCESSING
ENGINE
TM
CORTEX-A5
PROCESSOR
DATA PROCESSING UNIT (DPU)
PREFETCH UNIT AND BRANCH PREDICTOR (PFU)
DATA MICRO-TLB
INSTRUCTION MICRO-TLB
DATA STORE
BUFFER (STB)
DATA CACHE
UNIT (DCU)
32 KB
MAIN TRANSMISSION
LOOKINSIDE BUFFER (TLB)
INSTRUCTION CACHE
UNIT (ICU)
32 KB
BUS INTERFACE UNIT (BIU)
A5 BUS MASTER PORT
GENERIC INTERRUPT
CONTROLLER
(PrimeCell
®
PL-390)
L2 CACHE
CONTROLLER
(CoreLink
TM
PL-310)
256 KB
DATA MASTER PORTS
SHARC PROCESSORS
SYSTEM FABRIC
TO OTHER CORES
Figure 2. ARM Cortex A-5 Processor Block Diagram
Rev. PrF
|
Page 5 of 168 |
February 2016
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