Datasheet> 器件分类 > 存储> 存储> IS43TR16256AL-125KBLI

IS43TR16256AL-125KBLI: 产品描述DDR DRAM, 256MX16, 0.1ns, CMOS, PBGA96, 9 X 13 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-96; 产品类别存储存储; 文件大小3MB，共88页; 制造商Integrated Silicon Solution ( ISSI ); 标准

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IS43TR16256AL-125KBLI概述

DDR DRAM, 256MX16, 0.1ns, CMOS, PBGA96, 9 X 13 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-96

IS43TR16256AL-125KBLI规格参数

参数名称	属性值
是否Rohs认证	符合
包装说明	TFBGA,
Reach Compliance Code	compliant
Is Samacsys	N
访问模式	MULTI BANK PAGE BURST
最长访问时间	0.1 ns
其他特性	PROGRAMMABLE CAS LATENCY; AUTO/SELF REFRESH
JESD-30 代码	R-PBGA-B96
JESD-609代码	e1
长度	13 mm
内存密度	4294967296 bit
内存集成电路类型	DDR DRAM
内存宽度	16
功能数量	1
端口数量	1
端子数量	96
字数	268435456 words
字数代码	256000000
工作模式	SYNCHRONOUS
最高工作温度	85 °C
最低工作温度	-40 °C
组织	256MX16
封装主体材料	PLASTIC/EPOXY
封装代码	TFBGA
封装形状	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH
座面最大高度	1.2 mm
自我刷新	YES
最大供电电压 (Vsup)	1.45 V
最小供电电压 (Vsup)	1.283 V
标称供电电压 (Vsup)	1.35 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL
端子节距	0.8 mm
端子位置	BOTTOM
宽度	9 mm
Base Number Matches	1

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IS43/46TR16256A, IS43/46TR16256AL,

IS43/46TR85120A, IS43/46TR85120AL

512Mx8, 256Mx16 4Gb DDR3 SDRAM

MAY 2017

FEATURES



Standard Voltage:

and V

DDQ

= 1.5V ± 0.075V



Low Voltage (L):

and V

DDQ

= 1.35V + 0.1V, -0.067V

- Backward compatible to 1.5V



High speed data transfer rates with system

frequency up to 1066 MHz



8 internal banks for concurrent operation



8n-Bit pre-fetch architecture



Programmable CAS Latency



Programmable Additive Latency: 0, CL-1,CL-2



Programmable CAS WRITE latency (CWL) based

on tCK



Programmable Burst Length: 4 and 8



Programmable Burst Sequence: Sequential or

Interleave



BL switch on the fly



Auto Self Refresh(ASR)



Self Refresh Temperature(SRT)



Refresh Interval:

7.8 us (8192 cycles/64 ms) Tc= -40°C to 85°C

3.9 us (8192 cycles/32 ms) Tc= 85°C to 105°C



Partial Array Self Refresh

Asynchronous RESET pin

TDQS (Termination Data Strobe) supported (x8

only)

OCD (Off-Chip Driver Impedance Adjustment)

Dynamic ODT (On-Die Termination)

Driver strength : RZQ/7, RZQ/6 (RZQ = 240 Ω)

Write Leveling

Up to 200 MHz in DLL off mode

Operating temperature:

Commercial (T

= 0°C to +95°C)

Industrial (T

= -40°C to +95°C)

Automotive, A1 (T

= -40°C to +95°C)

Automotive, A2 (T

= -40°C to +105°C)

OPTIONS



Configuration:

512Mx8

256Mx16



Package:

96-ball BGA (9mm x 13mm) for x16

78-ball BGA (9mm x 10.5mm) for x8

ADDRESS TABLE

Parameter

Row Addressing

Column Addressing

Bank Addressing

Page size

Auto Precharge

Addressing

BL switch on the fly

512Mx8

A0-A15

A0-A9

BA0-2

1KB

A10/AP

A12/BC#

256Mx16

A0-A14

A0-A9

BA0-2

2KB

A10/AP

A12/BC#

SPEED BIN

Speed Option

JEDEC Speed Grade

CL-nRCD-nRP

tRCD,tRP(min)

15H

DDR3-1333H

9-9-9

13.5

125K

DDR3-1600K

11-11-11

13.75

107M

DDR3-1866M

13-13-13

13.91

093N

Units

DDR3-2133N

14-14-14

13.09

tCK

Note:Faster speed options are backward compatible to slower speed options.

without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised

to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product

can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use

in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc.

– www.issi.com –

Rev. I

04/27/2017

IS43/46TR16256A, IS43/46TR16256AL,

IS43/46TR85120A, IS43/46TR85120AL

1.3 Pinout Description - JEDEC Standard

Symbol

CK, CK#

CKE

Type

Input

Function

Clock: CK and CK# are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and negative edge of CK#.

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device

input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self-

Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is

asynchronous for Self-Refresh exit. After VREFCA and VREFDQ have become stable during the

power on and initialization sequence, they must be maintained during all operations (including

Self-Refresh). CKE must be maintained high throughout read and write accesses. Input buffers,

excluding CK, CK#, ODT and CKE, are disabled during power-down. Input buffers, excluding

CKE, are disabled during Self-Refresh.

Chip Select: All commands are masked when CS# is registered HIGH. CS# provides for external

Rank selection on systems with multiple Ranks. CS# is considered part of the command code.

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR3

SDRAM. When enabled, ODT is only applied to each DQ, DQSU, DQSU#, DQSL, DQSL#, DMU,

and DML signal. The ODT pin will be ignored if MR1 and MR2 are programmed to disable RTT.

Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being entered.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH coincident with that input data during a Write access. DM is sampled on both

edges of DQS. For x8 device, the function of DM or TDQS/TDQS# is enabled by Mode Register

A11 setting in MR1.

Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write, or Precharge

command is being applied. Bank address also determines which mode register is to be accessed

during a MRS cycle.

Address Inputs: Provide the row address for Active commands and the column address for Read/

Write commands to select one location out of the memory array in the respective bank. (A10/AP

and A12/BC# have additional functions; see below). The address inputs also provide the op-code

during Mode Register Set commands.

Auto-precharge: A10 is sampled during Read/Write commands to determine whether

Autoprecharge should be performed to the accessed bank after the Read/Write operation.

(HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command

to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If

only one bank is to be precharged, the bank is selected by bank addresses.

Burst Chop: A12 / BC# is sampled during Read and Write commands to determine if burst chop

(on-the-fly) will be performed. (HIGH, no burst chop; LOW: burst chopped). See command truth

table for details.

Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive when

RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a CMOS rail- to-

rail signal with DC high and low at 80% and 20% of VDD, i.e., 1.20V for DC high and 0.30V for

DC low.

Data Input/ Output: Bi-directional data bus.

Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered

in write data. For the x16, DQSL corresponds to the data on DQL0-DQL7; DQSU corresponds to

the data on DQU0-DQU7. The data strobes DQS, DQSL, and DQSU are paired with differential

signals DQS#, DQSL#, and DQSU#, respectively, to provide differential pair signaling to the

system during reads and writes. DDR3 SDRAM supports differential data strobe only and does

not support single-ended.

Termination Data Strobe: TDQS/TDQS# is applicable for x8 DRAMs only. When enabled via

Mode Register A11 = 1 in MR1, the DRAM will enable the same termination resistance function

on TDQS/TDQS# that is applied to DQS/DQS#. When disabled via mode register A11 = 0 in

MR1, DM/TDQS will provide the data mask function and TDQS# is not used. x16 DRAMs must

disable the TDQS function via mode register A11 = 0 in MR1.

No Connect: No internal electrical connection is present.

DQ Power Supply: 1.5 V +/- 0.075 V for standard voltage or 1.35V +0.1V, -0.067V for low voltage

CS#

ODT

Input

RAS#. CAS#.

WE#

DM, (DMU),

(DML)

Input

BA0 - BA2

Input

A0 - A15

Input

A10 / AP

Input

A12 / BC#

Input

RESET#

Input

DQ( DQL, DQU)

DQS,

DQS#, DQSU,

DQSU#, DQSL,

DQSL#

Input / Output

TDQS, TDQS#

Output

VDDQ

Supply

Integrated Silicon Solution, Inc.

– www.issi.com –

Rev. I

04/27/2017

IS43TR16256AL-125KBLI相似产品对比

	IS43TR16256AL-125KBLI	IS43TR16256A-125KBLI	IS43TR16256A-15HBLI	IS43TR16256AL-125KBL	IS46TR16256A-125KBLA2	IS46TR16256AL-15HBLA2	IS43TR16256A-15HBL	IS43TR16256AL-15HBLI	IS43TR85120AL-15HBL
描述	DDR DRAM, 256MX16, 0.1ns, CMOS, PBGA96, 9 X 13 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-96	DDR DRAM, 256MX16, 0.1ns, CMOS, PBGA96, FBGA-96	DDR DRAM, 256MX16, 0.125ns, CMOS, PBGA96, FBGA-96	DDR DRAM, 256MX16, 0.1ns, CMOS, PBGA96, 9 X 13 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-96	DDR DRAM, 256MX16, 0.1ns, CMOS, PBGA96, FBGA-96	DDR DRAM, 256MX16, 0.125ns, CMOS, PBGA96, 9 X 13 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-96	DDR DRAM, 256MX16, 0.125ns, CMOS, PBGA96, FBGA-96	DDR DRAM, 256MX16, 0.125ns, CMOS, PBGA96, 9 X 13 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-96	DDR DRAM, 512MX8, 0.255ns, CMOS, PBGA78, 9 X 10.50 MM, 0.80 MM PITCH, LEAD FREE, FBGA-78
包装说明	TFBGA,	TFBGA,	TFBGA,	TFBGA,	TFBGA, BGA96,9X16,32	TFBGA, BGA96,9X16,32	TFBGA,	TFBGA,	TFBGA,
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compli	compli	unknow
访问模式	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
最长访问时间	0.1 ns	0.1 ns	0.125 ns	0.1 ns	0.1 ns	0.125 ns	0.125 ns	0.125 ns	0.255 ns
其他特性	PROGRAMMABLE CAS LATENCY; AUTO/SELF REFRESH	PROGRAMMABLE CAS LATENCY; AUTO/SELF REFRESH	PROGRAMMABLE CAS LATENCY; AUTO/SELF REFRESH	PROGRAMMABLE CAS LATENCY; AUTO/SELF REFRESH	PROGRAMMABLE CAS LATENCY; AUTO/SELF REFRESH	PROGRAMMABLE CAS LATENCY; AUTO/SELF REFRESH	PROGRAMMABLE CAS LATENCY; AUTO/SELF REFRESH	PROGRAMMABLE CAS LATENCY; AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 代码	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96	R-PBGA-B78
长度	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm	13 mm	10.5 mm
内存密度	4294967296 bit	4294967296 bit	4294967296 bit	4294967296 bit	4294967296 bit	4294967296 bit	4294967296 bi	4294967296 bi	4294967296 bi
内存集成电路类型	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
内存宽度	16	16	16	16	16	16	16	16	8
功能数量	1	1	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1	1	1
端子数量	96	96	96	96	96	96	96	96	78
字数	268435456 words	268435456 words	268435456 words	268435456 words	268435456 words	268435456 words	268435456 words	268435456 words	536870912 words
字数代码	256000000	256000000	256000000	256000000	256000000	256000000	256000000	256000000	512000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	85 °C	85 °C	85 °C	105 °C	105 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-	-40 °C	-40 °C	-	-40 °C	-
组织	256MX16	256MX16	256MX16	256MX16	256MX16	256MX16	256MX16	256MX16	512MX8
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA	TFBGA
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
座面最大高度	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
自我刷新	YES	YES	YES	YES	YES	YES	YES	YES	YES
最大供电电压 (Vsup)	1.45 V	1.575 V	1.575 V	1.45 V	1.575 V	1.45 V	1.575 V	1.45 V	1.45 V
最小供电电压 (Vsup)	1.283 V	1.425 V	1.425 V	1.283 V	1.425 V	1.283 V	1.425 V	1.283 V	1.283 V
标称供电电压 (Vsup)	1.35 V	1.5 V	1.5 V	1.35 V	1.5 V	1.35 V	1.5 V	1.35 V	1.35 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	OTHER	INDUSTRIAL	INDUSTRIAL	OTHER	INDUSTRIAL	OTHER
端子形式	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
宽度	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm	9 mm
是否Rohs认证	符合	符合	符合	符合	符合	符合	符合	符合	-
厂商名称	-	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	-	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )
Factory Lead Time	-	6 weeks	6 weeks	6 weeks	8 weeks	8 weeks	6 weeks	6 weeks	13 weeks 6 days

IS43TR16256AL-125KBLI

IS43TR16256AL-125KBLI在线购买

IS43TR16256AL-125KBLI概述

IS43TR16256AL-125KBLI规格参数

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IS43TR16256AL-125KBLI相似产品对比

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