128-deep transmitter and receiver FIFOs. Deep FIFOs
reduce CPU overhead and allow utilisation of higher data
rates.
It is software compatible with the widely used industry-
standard 16C550 type devices and compatibles, as well as
other OX16C95x family devices.
In addition to increased performance and FIFO size, the
OXCF950 rev B also provides enhanced features including
improved flow control. Automated software flow control
using Xon/Xoff and automated hardware flow control using
CTS#/RTS# and DSR#/DTR# prevent FIFO over-run. Flow
control and interrupt thresholds are fully programmable and
readable, enabling programmers to fine-tune the
performance of their system. FIFO levels are readable to
facilitate fast driver applications.
The addition of software reset enables recovery from
unforeseen error conditions allowing drivers to restart
gracefully. The OXCF950 rev B supports 9-bit data frames
used in multi-drop industrial protocols. It also offers multiple
external clock options for isochronous applications, e.g.
ISDN, xDSL.
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The OXCF950 rev B also incorporates a bridge to an 8 bit
Local Bus in Local Bus Mode. It allows card developers to
expand the capabilities of their products by adding
peripherals to this bus. In addition, two user IO pins are
included to enhance external device control. These IO pins
can also be configured as interrupt inputs.
OXCF950 rev B DATA SHEET
mode (pin or EEPROM selectable) allows the device to
function in embedded systems where the generic device
driver present assumes I/O occupancy of 8 byte
addresses, without any additional components. The second
mode (pin selectable) allows the device to act as a stand-
alone 16C950 type part with the benefits over the 16C950
rev B of 5V tolerance, and packaging options where pin-
compatibility with 550 type UARTs is not required.
The OXCF950 rev B fixes all known errata of the OXCF950
part. It also adds two new modes of operation. The first
S
UMMARY OF
D
IFFERENCES BETWEEN
OXCF950
AND
OXCF950
REV
B
The OXCF950 rev B has been designed to be as compatible as possible with the rev A part. A designer considering switching to
the new device should be aware of the following –
•
•
•
•
•
•
•
•
•
•
•
Power supply. The new part has a supply voltage range from 2.7V to 3.6V. The original part had a supply voltage
range from 3.15V to 5.25V. A new design requiring operation at both 3.3V and 5V will require an in-line low voltage-
drop regulator.
Pin compatible (other than supply voltage constraints).
Software compatible – all the modes of the original CF950 are available in the rev B device.
All I/Os are now 5V tolerant, with the exception of the Crystal oscillator input.
The crystal oscillator circuit is only suitable for frequencies up to 20 MHz. For operation above this frequency, an
external clock source is required.
A new ‘generic’ mode has been added allowing generic drivers to access the UART without needing external circuitry
to adjust the address ranges. This mode (8 byte I/O space) can be selected either by pin control or through the
EEPROM. Access to configuration registers is still possible via a software paging technique.
A stand-alone 16C950 type mode has been added (pin selectable) to allow the device to be used where pin-
compatibility with 16C550 type devices is not required.
All known errata in the original OXCF950 have been fixed.
The device is now characterised for an extended operating temperature range of –40C to +105C.
The CF950 rev B is additionally available in a 48 TFBGA package.
The input clock frequency may be restricted by the CF950 rev B environment. Where an external EEPROM is being
used, the maximum clock frequency of the external EEPROM multiplied by 64 will give a input clock frequency limit.
For an external EEPROM powered off 5V with a maximum frequency of 1MHz, this sets no limits. An EEPROM
powered off 2.7V may typically have a maximum frequency of 250 kHz, which would restrict the CF950 rev B input
frequency to 16 MHz.
Software can identify the difference between an OXCF950 and an OXCF950 rev B by reading the UART REV register (see
6.11.7)
For the original OXCF950 this reads 0x06, for the OXCF950 rev B this reads 0x08.
Throughout this document, the OXCF950 rev B will henceforth simply be referred to as the OXCF950.
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OXCF950 rev B DATA SHEET
C
ONTENTS
FEATURES ................................................................................................................................................... 1
NORMAL/LOCAL BUS MODES.................................................................................................................................... 11
CONFIGURATION SPACE (CARD INFORMATION STRUCTURE)................................................................................ 13
LOCAL BUS MODE SPACE MAP ................................................................................................................................ 13
NORMAL MODE SPACE MAP ..................................................................................................................................... 14
ACCESS TO IO FUNCTION ............................................................................................................................................. 14
ACCESS TO INTERNAL UART .................................................................................................................................... 14
ACCESS TO LOCAL BUS ............................................................................................................................................ 14
ACCESSING LOCAL CONFIGURATION REGISTERS ............................................................................................... 15
SOCKET AND COPY REGISTER ‘SCR’ (OFFSET 0XFE)........................................................................................... 23
CARD INFORMATION STRUCTURE............................................................................................................................... 23
LOCAL BUS MODE ...................................................................................................................................................... 23
NORMAL MODE ........................................................................................................................................................... 25
GENERIC NORMAL MODE.......................................................................................................................................... 27
FIFO CONTROL REGISTER ‘FCR’ .............................................................................................................................. 36
6.5
LINE CONTROL & STATUS............................................................................................................................................. 37
6.5.1
FALSE START BIT DETECTION.................................................................................................................................. 37
6.5.2
LINE CONTROL REGISTER ‘LCR’............................................................................................................................... 37
6.5.3
LINE STATUS REGISTER ‘LSR’ .................................................................................................................................. 37
INTERRUPT STATUS REGISTER ‘ISR’....................................................................................................................... 40
MODEM CONTROL REGISTER ‘MCR’........................................................................................................................ 41
6.7.2
MODEM STATUS REGISTER ‘MSR’ ........................................................................................................................... 42
6.8
OTHER STANDARD REGISTERS ................................................................................................................................... 42
ENHANCED FEATURES REGISTER ‘EFR’................................................................................................................. 42
6.9.2
SPECIAL CHARACTER DETECTION .......................................................................................................................... 43
6.9.3
AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................... 44
6.9.4
AUTOMATIC OUT-OF-BAND FLOW CONTROL ......................................................................................................... 44
GENERAL OPERATION ............................................................................................................................................... 44
TIMES CLOCK REGISTER ‘TCR’................................................................................................................................. 45
6.11 ADDITIONAL FEATURES ................................................................................................................................................ 47
6.11.1
ADDITIONAL STATUS REGISTER ‘ASR’ .................................................................................................................... 47
6.11.2
FIFO FILL LEVELS ‘TFL & RFL’ ................................................................................................................................... 48
6.11.3
ADDITIONAL CONTROL REGISTER ‘ACR’................................................................................................................. 48
6.11.12 GOOD-DATA STATUS REGISTER ‘GDS’.................................................................................................................... 52
6.11.13 DMA STATUS REGISTER ‘DMS’ ................................................................................................................................. 52
6.11.14 PORT INDEX REGISTER ‘PIX’..................................................................................................................................... 52
6.11.16 MISC DATA REGISTER ............................................................................................................................................... 52
7
7.1
7.2
7.3
7.4
7.5
SERIAL EEPROM SPECIFICATION ................................................................................................... 53
EEPROM DATA ORGANISATION ................................................................................................................................... 53
ZONE 0: HEADER ............................................................................................................................................................ 53
ZONE 1: CARD INFORMATION STRUCTURE................................................................................................................ 54
ZONE 2: LOCAL REGISTER CONFIGURATION ............................................................................................................ 54
ZONE 3: FUNCTION ACCESS (UART)............................................................................................................................ 55
DC ELECTRICAL CHARACTERISTICS ............................................................................................. 57
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OXFORD SEMICONDUCTOR, INC.
9.1
9.2
OXCF950 rev B DATA SHEET
3.0V TO 3.6V OPERATION............................................................................................................................................... 57