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OXCF950-TQ-B: 产品描述low cost asynchronous 16-bit PC card or Compact Flash UART device; 文件大小375KB，共66页; 制造商Oxford; 官网地址http://www.oxsemi.com

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OXCF950-TQ-B概述

low cost asynchronous 16-bit PC card or Compact Flash UART device

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OXCF950 rev B

DATA SHEET

EATURES

•

Single full-duplex asynchronous channel

128-byte deep transmitter / receiver FIFO

Fully software compatible with industry standard

16C550 type UARTs

Readable FIFO levels

System clock up to 60MHz

Flexible clock prescaler from 1 to 31.875

9-bit data framing as well as 5,6,7 and 8

Detection of bad data in the receiver FIFO

Automated in-band flow control using programmable

Xon/Xoff characters

Transmitter and receiver can be disabled

Low power CMOS

3.3V operation, 5V tolerant I/O

Extended temperature range –40C to +105C

Software compatible with OXCF950

16C950 mode for local bus applications

Generic embedded driver compatibility mode

•

Programmable by external Microwire

EEPROM

(EEPROM programmed via Oxford Semiconductor

utilities).

Extremely low power consumption by use of

asynchronous UART core and power down (sleep)

modes

Range of packages -Ultra small 48 pin TQFP package

or a 48 ball TFBGA.

Supports all UART types 450 up to 950 (fully

programmable)

CF+ Compliant (Revision 1.4).

16-bit PC Card Compliant (PCMCIA Revision 7.1)

8 bit Local Bus interface included for PCMCIA

applications

2 Multi-purpose I/O pins which can be configured as

interrupt inputs

ESCRIPTION

The OXCF950 rev B is a low cost asynchronous 16-bit PC

card (henceforth referred to as PCMCIA) or Compact Flash

(henceforth referred to as CF) UART (and Local Bus)

device. Local Bus Selection is performed by use of a

MODE pin. Note that Local Bus mode uses indirect

addressing, which is only supported by PCMCIA.

The 3.3V technology has been specified to operate as low

as 2.7 V to allow an in-line regulator to be used for mixed

3V/5V applications. All the I/Os are 5V tolerant with the

exception of the clock/crystal oscillator input.

The EEPROM interface allows the programming of the

Attribute Memory, UART and Local Configuration Registers

during power up or hard/soft reset. This allows different

card manufacturers to modify the information contained in

the Attribute memory or UART/registers as required, for

example PC-Card ID value.

A number of power-down modes are included to keep

power consumption to a minimum. Such features include

clock division (fully programmable) and sleep modes when

a function of the OXCF950 rev B is not being used.

The OXCF950 rev B contains a single-channel ultra-high

performance UART offering data rates up to 15Mbps and

Oxford Semiconductor, Inc.

25 Milton Park, Abingdon, Oxon,

OX14 4SH, UK

Tel: +44 (0)1235 824900

Oxford Semiconductor 2006

OXCF950 DS-0027—Feb 2006

Part Nos. OXCF950-TQ-B

OXCF950-TB-B

OXCF950-TQBG

128-deep transmitter and receiver FIFOs. Deep FIFOs

reduce CPU overhead and allow utilisation of higher data

rates.

It is software compatible with the widely used industry-

standard 16C550 type devices and compatibles, as well as

other OX16C95x family devices.

In addition to increased performance and FIFO size, the

OXCF950 rev B also provides enhanced features including

improved flow control. Automated software flow control

using Xon/Xoff and automated hardware flow control using

CTS#/RTS# and DSR#/DTR# prevent FIFO over-run. Flow

control and interrupt thresholds are fully programmable and

readable, enabling programmers to fine-tune the

performance of their system. FIFO levels are readable to

facilitate fast driver applications.

The addition of software reset enables recovery from

unforeseen error conditions allowing drivers to restart

gracefully. The OXCF950 rev B supports 9-bit data frames

used in multi-drop industrial protocols. It also offers multiple

external clock options for isochronous applications, e.g.

ISDN, xDSL.

External—Free Release

OXFORD SEMICONDUCTOR, INC.

The OXCF950 rev B also incorporates a bridge to an 8 bit

Local Bus in Local Bus Mode. It allows card developers to

expand the capabilities of their products by adding

peripherals to this bus. In addition, two user IO pins are

included to enhance external device control. These IO pins

can also be configured as interrupt inputs.

OXCF950 rev B DATA SHEET

mode (pin or EEPROM selectable) allows the device to

function in embedded systems where the generic device

driver present assumes I/O occupancy of 8 byte

addresses, without any additional components. The second

mode (pin selectable) allows the device to act as a stand-

alone 16C950 type part with the benefits over the 16C950

rev B of 5V tolerance, and packaging options where pin-

compatibility with 550 type UARTs is not required.

The OXCF950 rev B fixes all known errata of the OXCF950

part. It also adds two new modes of operation. The first

UMMARY OF

IFFERENCES BETWEEN

OXCF950

AND

OXCF950

REV

The OXCF950 rev B has been designed to be as compatible as possible with the rev A part. A designer considering switching to

the new device should be aware of the following –

•

Power supply. The new part has a supply voltage range from 2.7V to 3.6V. The original part had a supply voltage

range from 3.15V to 5.25V. A new design requiring operation at both 3.3V and 5V will require an in-line low voltage-

drop regulator.

Pin compatible (other than supply voltage constraints).

Software compatible – all the modes of the original CF950 are available in the rev B device.

All I/Os are now 5V tolerant, with the exception of the Crystal oscillator input.

The crystal oscillator circuit is only suitable for frequencies up to 20 MHz. For operation above this frequency, an

external clock source is required.

A new ‘generic’ mode has been added allowing generic drivers to access the UART without needing external circuitry

to adjust the address ranges. This mode (8 byte I/O space) can be selected either by pin control or through the

EEPROM. Access to configuration registers is still possible via a software paging technique.

A stand-alone 16C950 type mode has been added (pin selectable) to allow the device to be used where pin-

compatibility with 16C550 type devices is not required.

All known errata in the original OXCF950 have been fixed.

The device is now characterised for an extended operating temperature range of –40C to +105C.

The CF950 rev B is additionally available in a 48 TFBGA package.

The input clock frequency may be restricted by the CF950 rev B environment. Where an external EEPROM is being

used, the maximum clock frequency of the external EEPROM multiplied by 64 will give a input clock frequency limit.

For an external EEPROM powered off 5V with a maximum frequency of 1MHz, this sets no limits. An EEPROM

powered off 2.7V may typically have a maximum frequency of 250 kHz, which would restrict the CF950 rev B input

frequency to 16 MHz.

Software can identify the difference between an OXCF950 and an OXCF950 rev B by reading the UART REV register (see

6.11.7)

For the original OXCF950 this reads 0x06, for the OXCF950 rev B this reads 0x08.

Throughout this document, the OXCF950 rev B will henceforth simply be referred to as the OXCF950.

DS-0027 Feb 06

External—Free Release

Page 2 of 66

OXFORD SEMICONDUCTOR, INC.

OXCF950 rev B DATA SHEET

ONTENTS

FEATURES ................................................................................................................................................... 1

DESCRIPTION .............................................................................................................................................. 1

SUMMARY OF DIFFERENCES BETWEEN OXCF950 AND OXCF950 REV B........................................... 2

CONTENTS................................................................................................................................................... 3

REVISION HISTORY..................................................................................................................................... 5

4.1

4.1.1

4.1.2

4.1.3

4.2

BLOCK DIAGRAM ................................................................................................................................ 6

PIN INFORMATION ............................................................................................................................... 7

PIN DESCRIPTIONS.............................................................................................................................. 8

CONFIGURATION & OPERATION ..................................................................................................... 11

MODE SELECTION .......................................................................................................................................................... 11

GENERIC MODE .......................................................................................................................................................... 11

16C950 MODE .............................................................................................................................................................. 11

NORMAL/LOCAL BUS MODES.................................................................................................................................... 11

PCMCIA/CF OPERATION ................................................................................................................................................ 11

5.1

5.2

5.2.1

5.2.2

5.3

5.3.1

5.3.2

5.3.3

5.4

5.4.1

5.4.2

5.5

5.5.1

5.5.2

5.5.3

5.5.4

5.6

5.6.1

5.6.2

5.6.3

PCMCIA / CF TARGET CONTROLLER .............................................................................................. 13

OPERATION ..................................................................................................................................................................... 13

CONFIGURATION SPACE (CARD INFORMATION STRUCTURE)................................................................................ 13

LOCAL BUS MODE SPACE MAP ................................................................................................................................ 13

NORMAL MODE SPACE MAP ..................................................................................................................................... 14

ACCESS TO IO FUNCTION ............................................................................................................................................. 14

ACCESS TO INTERNAL UART .................................................................................................................................... 14

ACCESS TO LOCAL BUS ............................................................................................................................................ 14

ACCESSING LOCAL CONFIGURATION REGISTERS ............................................................................................... 15

CF / PCMCIA INTERRUPT ............................................................................................................................................... 19

INTERRUPT GENERATION ......................................................................................................................................... 19

INTERRUPT SOURCES ............................................................................................................................................... 19

CF/PCMCIA FUNCTION CONFIGURATION REGISTERS .............................................................................................. 20

CONFIGURATION OPTIONS REGISTER ‘COR’ (OFFSET 0XF8).............................................................................. 20

CONFIGURATION STATUS REGISTER ‘CSR’ (OFFSET 0XFA)................................................................................ 21

PIN REPLACEMENT REGISTER ‘PRR’ (OFFSET 0XFC) ........................................................................................... 22

SOCKET AND COPY REGISTER ‘SCR’ (OFFSET 0XFE)........................................................................................... 23

CARD INFORMATION STRUCTURE............................................................................................................................... 23

LOCAL BUS MODE ...................................................................................................................................................... 23

NORMAL MODE ........................................................................................................................................................... 25

GENERIC NORMAL MODE.......................................................................................................................................... 27

6.1

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.2

6.3

6.3.1

6.3.2

INTERNAL 950 UART ......................................................................................................................... 30

MODE SELECTION .......................................................................................................................................................... 30

450 MODE..................................................................................................................................................................... 30

550 MODE..................................................................................................................................................................... 30

750 MODE..................................................................................................................................................................... 30

650 MODE..................................................................................................................................................................... 30

950 MODE..................................................................................................................................................................... 30

REGISTER DESCRIPTION TABLES ............................................................................................................................... 32

RESET CONFIGURATION ............................................................................................................................................... 35

HOST RESET ............................................................................................................................................................... 35

SOFTWARE RESET ..................................................................................................................................................... 35

External—Free Release

Page 3 of 66

DS-0027 Feb 06

OXFORD SEMICONDUCTOR, INC.

OXCF950 rev B DATA SHEET

6.4

TRANSMITTER & RECEIVER FIFOS .............................................................................................................................. 35

6.4.1

FIFO CONTROL REGISTER ‘FCR’ .............................................................................................................................. 36

6.5

LINE CONTROL & STATUS............................................................................................................................................. 37

6.5.1

FALSE START BIT DETECTION.................................................................................................................................. 37

6.5.2

LINE CONTROL REGISTER ‘LCR’............................................................................................................................... 37

6.5.3

LINE STATUS REGISTER ‘LSR’ .................................................................................................................................. 37

6.6

INTERRUPTS & SLEEP MODE........................................................................................................................................ 39

6.6.1

INTERRUPT ENABLE REGISTER ‘IER’....................................................................................................................... 39

6.6.2

INTERRUPT STATUS REGISTER ‘ISR’....................................................................................................................... 40

6.6.3

INTERRUPT DESCRIPTION ........................................................................................................................................ 40

6.6.4

SLEEP MODE ............................................................................................................................................................... 41

6.7

MODEM INTERFACE ....................................................................................................................................................... 41

6.7.1

MODEM CONTROL REGISTER ‘MCR’........................................................................................................................ 41

6.7.2

MODEM STATUS REGISTER ‘MSR’ ........................................................................................................................... 42

6.8

OTHER STANDARD REGISTERS ................................................................................................................................... 42

6.8.1

DIVISOR LATCH REGISTERS ‘DLL & DLM’................................................................................................................ 42

6.8.2

SCRATCH PAD REGISTER ‘SPR’ ............................................................................................................................... 42

6.9

AUTOMATIC FLOW CONTROL....................................................................................................................................... 42

6.9.1

ENHANCED FEATURES REGISTER ‘EFR’................................................................................................................. 42

6.9.2

SPECIAL CHARACTER DETECTION .......................................................................................................................... 43

6.9.3

AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................... 44

6.9.4

AUTOMATIC OUT-OF-BAND FLOW CONTROL ......................................................................................................... 44

6.10 BAUD RATE GENERATION............................................................................................................................................. 44

6.10.1

GENERAL OPERATION ............................................................................................................................................... 44

6.10.2

CLOCK PRESCALER REGISTER ‘CPR’...................................................................................................................... 45

6.10.3

TIMES CLOCK REGISTER ‘TCR’................................................................................................................................. 45

6.10.4

INPUT CLOCK OPTIONS ............................................................................................................................................. 46

6.10.5

TTL CLOCK MODULE .................................................................................................................................................. 46

6.10.6

EXTERNAL 1X CLOCK MODE..................................................................................................................................... 47

6.10.7

CRYSTAL OSCILLATOR CIRCUIT .............................................................................................................................. 47

6.11 ADDITIONAL FEATURES ................................................................................................................................................ 47

6.11.1

ADDITIONAL STATUS REGISTER ‘ASR’ .................................................................................................................... 47

6.11.2

FIFO FILL LEVELS ‘TFL & RFL’ ................................................................................................................................... 48

6.11.3

ADDITIONAL CONTROL REGISTER ‘ACR’................................................................................................................. 48

6.11.4

TRANSMITTER TRIGGER LEVEL ‘TTL’ ...................................................................................................................... 49

6.11.5

RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ...................................................................................................... 49

6.11.6

FLOW CONTROL LEVELS ‘FCL & FCH’...................................................................................................................... 49

6.11.7

DEVICE IDENTIFICATION REGISTERS...................................................................................................................... 50

6.11.8

CLOCK SELECT REGISTER ‘CKS’.............................................................................................................................. 50

6.11.9

NINE-BIT MODE REGISTER ‘NMR’ ............................................................................................................................. 50

6.11.10 MODEM DISABLE MASK ‘MDM’ .................................................................................................................................. 51

6.11.11 READABLE FCR ‘RFC’................................................................................................................................................. 51

6.11.12 GOOD-DATA STATUS REGISTER ‘GDS’.................................................................................................................... 52

6.11.13 DMA STATUS REGISTER ‘DMS’ ................................................................................................................................. 52

6.11.14 PORT INDEX REGISTER ‘PIX’..................................................................................................................................... 52

6.11.15 CLOCK ALTERATION REGISTER ‘CKA’ ..................................................................................................................... 52

6.11.16 MISC DATA REGISTER ............................................................................................................................................... 52

7.1

7.2

7.3

7.4

7.5

SERIAL EEPROM SPECIFICATION ................................................................................................... 53

EEPROM DATA ORGANISATION ................................................................................................................................... 53

ZONE 0: HEADER ............................................................................................................................................................ 53

ZONE 1: CARD INFORMATION STRUCTURE................................................................................................................ 54

ZONE 2: LOCAL REGISTER CONFIGURATION ............................................................................................................ 54

ZONE 3: FUNCTION ACCESS (UART)............................................................................................................................ 55

OPERATING CONDITIONS................................................................................................................. 56

DC ELECTRICAL CHARACTERISTICS ............................................................................................. 57

External—Free Release

Page 4 of 66

DS-0027 Feb 06

OXCF950-TQ-B相似产品对比

	OXCF950-TQ-B	OXCF950-TB-B	OXCF950	OXCF950_06	OXCF950-TQBG	OXCF950-TBBG
描述	low cost asynchronous 16-bit PC card or Compact Flash UART device	low cost asynchronous 16-bit PC card or Compact Flash UART device	low cost asynchronous 16-bit PC card or Compact Flash UART device	low cost asynchronous 16-bit PC card or Compact Flash UART device	low cost asynchronous 16-bit PC card or Compact Flash UART device	low cost asynchronous 16-bit PC card or Compact Flash UART device

OXCF950-TQ-B

OXCF950-TQ-B概述

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