NJU6433B
PRELIMINARY
1/4 DUTY LCD DRIVER
!
GENERAL DESCRIPTION
The NJU6433B is a 1/4 duty LCD driver for segment type
LCD panel.
The LCD driver consists of 4-common and 50-segment
drives up to 200 segments.
The NJU6433B is useful for the digital tuning system or
others segment type display driver.
!
PACKAGE OUTLINE
NJU6433BFG1
NJU6433BFH1
!
FEATURES
#
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#
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50 Segment Drivers
Duty Ratio 1/4 (Up to 200-Segments)
Serial Data Transmission (Shift Clock 2MHz max.)
Oscillation Circuit On-chip (External Resistance Required)
Display Off Function (INHb Terminal)
Operating Voltage
2.4 to 5.5V
LCD Driving Voltage
6.5V Max.
Package Outline
Bump Chip, Chip, QFP 64-G1, QFP64-H1
C-MOS Technology
NJU6433BC/BCH
!
BLOCK DIAGRAM
Ver.2005-07-08
-1-
NJU6433B
!
PAD LOCATION
48
49
33
32
Y
Chip Center
Chip Size
Chip Thickness
PAD Size
PAD Pitch
Bump Height
: X=0µm, Y=0µm
: X=3.20 mm, Y=3.20 mm
: 400
µm
: X=99.2
µm,
Y=99.2
µm
: 171.2
µm
: 25
µm
X
64
1
16
17
!
PAD COORDINATES
PAD
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
X=
µm
-1279
-1107
-936
-765
-594
-423
-251
-80
91
262
433
605
776
947
1118
1289
1437
1437
1437
1437
1437
1437
1437
1437
Y=
µm
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1288
-1117
-946
-775
-603
-432
-261
-90
PAD
No.
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Chip Size 3.20 x 3.20 mm(Chip Center
PAD
Terminal
X=
µm
Y=
µm
Terminal
No.
SEG
25
1437
81
49
SEG
49
SEG
26
1437
253
50
SEG
50
SEG
27
1437
424
51
OSC
1
SEG
28
1437
595
52
OSC
2
SEG
29
1437
766
53
V
DD
SEG
30
1437
937
54
V
SS
SEG
31
1437
1109
55
V
LCD
SEG
32
1437
1280
56
CE
SEG
33
1280
1437
57
SCL
SEG
34
1109
1437
58
DATA
SEG
35
937
1437
59
MODE
SEG
36
766
1437
60
INHX
SEG
37
595
1437
61
COM
4
SEG
38
424
1437
62
COM
3
SEG
39
253
1437
63
COM
2
SEG
40
81
1437
64
COM
1
SEG
41
-90
1437
SEG
42
-261
1437
SEG
43
-432
1437
SEG
44
-603
1437
SEG
45
-775
1437
SEG
46
-946
1437
SEG
47
-1117
1437
SEG
48
-1288
1437
X=0µm, Y=0µm)
X=
µm
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
-1437
Y=
µm
1280
1109
937
766
595
424
253
81
-90
-261
-432
-603
-775
-946
-1117
-1288
Terminal
SEG
1
SEG
2
SEG
3
SEG
4
SEG
5
SEG
6
SEG
7
SEG
8
SEG
9
SEG
10
SEG
11
SEG
12
SEG
13
SEG
14
SEG
15
SEG
16
SEG
17
SEG
18
SEG
19
SEG
20
SEG
21
SEG
22
SEG
23
SEG
24
-2-
Ver.2005-07-08
NJU6433B
!
PIN CONFIGURATION
B
!
TERMINAL DESCRIPTION
No.
1~50
51
52
53
54
55
SYMBOL
SEG
1
~SEG
50
OSC
1
OSC
2
V
DD
V
SS
V
LCD
FUNCTION
LCD Segment Output Terminals
Oscillation Terminals :
External resistance is connected to these terminals.
Power Supply (+5V)
Power Supply (0V)
Power Supply for LCD Driving
The relation : 1.3V
DD
≥
|V
DD
- V
LCD
|, V
SS
≥
V
LCD
must be maintained.
Chip Enable Signal Input Terminal :
"H" : LCD display data and mode setting data input
"L" : Disable
Fall Edge : LCD display data latch
Serial Data Transmission Clock Input Terminal :
LCD display and Mode setting data are input synchronized
SCL clock signal rise edge.
Serial Data Input Terminal
Data input timing : SCL clock rise edge
Data or Mode Select Terminal
"H" : Data input mode
"L" : LCD display data input mode
(Refer the mode setting table for mode setting contents)
Display-Off Control Terminal :
When display goes to off, the display data in the shift-register is
retained.
"H" : Display-On
"L" : Display-Off
LCD Common Output Terminals
56
CE
57
58
SCL
DATA
59
MODE
60
INHb
61~64
COM
4
~COM
1
Ver.2005-07-08
-3-
NJU6433B
!
FUNCTIONAL DESCRIPTION
(1) Operation of each block
(1-1) Oscillation Circuit
The oscillation circuit operate by connecting external resistance (capacitance is incorporated).
This circuit provides the clock signal to both common and segment drivers.
(1-2) Divider Circuit
This circuit divides the oscillating signal to generate the common and segment timing.
(1-3) Shift-Register
When the CE terminal is "H" (Enable mode), the display data is transferred to the shift-register
synchronized by the shift clock on the SCL terminal.
(1-4) Latch Circuit and Segment Driver
When the CE signal falling, the display data is latched, and the data controls the segment signal of
display-on/off.
(2) Data Input Format
(2-1) Input Data Correspond to Segment Status
The "H" input data correspond to segment "ON" and "L" correspond to "OFF".
Data Dxxx
”H”
”L”
Segment Status
ON
OFF
-4-
Ver.2005-07-08
NJU6433B
(2-2) Write to Shift-register
Write to shift-register performes Mode setting data writing and LCD display data writing.
Ver.2005-07-08
-5-