IS64LP12832
IS64LP12836, IS64LP25618
128K x 32, 128K x 36, 256K x 18
SYNCHRONOUS
PIPELINED STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Interleaved or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP and
119-pin PBGA package
• Power-down snooze mode
• Power Supply
+ 3.3V V
DD
+ 3.3V OR 2.5V V
DDQ
(I/O)
• Temperature offerings
Option A1: -40
0
C to +85
0
C
Option A2: -40
0
C to +105
0
C
Option A3: -40
0
C to +125
0
C
ISSI
®
ADVANCED INFORMATION
JANUARY 2003
DESCRIPTION
The
ISSI
IS64LP12832, IS64LP12836, and IS64LP25618
are high-speed synchronous static RAMs designed to
provide high-performance memory with burst for high-
speed networking and communication applications.
IS64LP12832 is organized as 131,072 words by 32 bits.
IS64LP12836 is organized as 131,072 words by 36 bits.
IS64LP25618 is organized as 262,144 words by 18 bits. The
IS64LP12832, IS64LP12836, and IS64LP25618 are fabri-
cated with
ISSI
's advanced CMOS technology. These
devices integrate a 2-bit burst counter, high-speed SRAM
core, and high-drive capability outputs into a single mono-
lithic circuit. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be from
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQa,
BW2
controls DQb,
BW3
controls
DQc,
BW4
controls DQd, conditioned by
BWE
being
LOW. A LOW on
GW
input would cause all bytes to be
written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frequency
-166
3.5
6
166
-150
3.8
6.7
150
Units
ns
ns
MHz
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
01/20/03
1
IS64LP12832
IS64LP12836, IS64LP25618
PIN CONFIGURATION
119-pin PBGA (Top View)
100-Pin TQFP
ISSI
A
A
CE
CE2
BW4
BW3
BW2
BW1
CE2
VDD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
®
1
A
VDDQ
B
NC
C
NC
D
DQc1
1
E
DQc2
2
F
VDDQ
G
DQc5
5
H
DQc7
7
J
VDDQ
K
1
DQd1
L
DQd4
4
M
VDDQ
N
DQd6
6
P
DQd8
8
R
NC
T
NC
U
VDDQ
2
3
4
5
6
7
6
A6
CE2
A7
7
NC
DQc3
3
DQc4
4
DQc6
6
DQc8
8
VDD
2
DQd2
DQd3
3
DQd5
5
DQd7
7
NC
A5
NC
NC
4
A4
A3
3
A2
2
GND
GND
GND
BW3
GND
NC
GND
BW4
GND
GND
GND
MODE
A10
10
NC
ADSP
ADSC
VDD
NC
CE
OE
ADV
GW
VDD
CLK
NC
BWE
A1
A0
VDD
11
A11
NC
8
A8
A9
9
A12
12
GND
GND
GND
BW2
GND
NC
GND
BW1
GND
GND
GND
NC
A14
14
NC
16
A16
CE2
A15
15
NC
DQb6
6
DQb5
5
DQb4
4
DQb2
2
VDD
7
DQa7
DQa5
5
DQa4
4
DQa3
3
NC
A13
13
NC
NC
VDDQ
NC
NC
8
DQb8
DQb7
7
VDDQ
DQb3
3
DQb1
1
VDDQ
8
DQa8
DQa6
6
VDDQ
DQa2
2
DQa1
1
NC
ZZ
VDDQ
NC
DQc
DQc
VDDQ
GND
DQc
DQc
DQc
DQc
GND
VDDQ
DQc
DQc
NC
VDD
NC
GND
DQd
DQd
VDDQ
GND
DQd
DQd
DQd
DQd
GND
VDDQ
DQd
DQd
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb
DQb
VDDQ
GND
DQb
DQb
DQb
DQb
GND
VDDQ
DQb
DQb
GND
NC
VDD
ZZ
DQa
DQa
VDDQ
GND
DQa
DQa
DQa
DQa
GND
VDDQ
DQa
DQa
NC
128K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Ad-
vance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW
CE, CE2,
CE2
OE
DQa-DQd
MODE
V
DD
GND
V
DDQ
ZZ
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V
or 2.5V
Snooze Enable
A
CLK
ADSP
ADSC
ADV
BW1-BW4
BWE
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
01/20/03
MODE
A
A
A
A
A1
A0
NC
NC
GND
VDD
NC
NC
A
A
A
A
A
A
A
3
IS64LP12832
IS64LP12836, IS64LP25618
PIN CONFIGURATION
119-pin PBGA (Top View)
1
A
VDDQ
B
NC
C
NC
D
DQc1
1
E
DQc2
2
F
VDDQ
G
5
DQc5
H
DQc7
7
J
VDDQ
K
DQd1
1
L
DQd4
4
M
VDDQ
N
DQd6
6
P
DQd8
8
R
NC
T
NC
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
NC
A10
10
11
A11
A14
14
NC
ZZ
A5
5
MODE
VDD
NC
A13
13
NC
DQPd
GND
A0
GND
DQPa
DQa1
1
DQd7
7
GND
A1
GND
DQa3
3
DQa2
2
DQd5
5
GND
DQd3
3
DQd2
2
GND
BW4
CLK
NC
BWE
GND
BW1
GND
DQa7
7
DQa5
5
DQa4
4
DQa8
8
DQa6
6
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
DQc8
8
GND
DQc6
6
DQc4
4
GND
BW3
DQc3
3
GND
DQPc
GND
NC
CE
OE
ADV
GW
GND
GND
GND
BW2
GND
DQPb
DQb6
6
DQb5
5
DQb4
4
DQb2
2
8
DQb8
DQb7
7
VDDQ
3
DQb3
DQb1
1
A7
7
A2
2
VDD
A12
12
A15
15
NC
CE2
A3
3
6
A6
4
A4
2
3
4
5
6
7
ISSI
100-Pin TQFP
A
A
CE
CE2
BW4
BW3
BW2
BW1
CE2
VDD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
®
ADSP
ADSC
8
A8
A9
9
16
A16
CE2
VDDQ
NC
DQPc
DQc
DQc
VDDQ
GND
DQc
DQc
DQc
DQc
GND
VDDQ
DQc
DQc
NC
VDD
NC
GND
DQd
DQd
VDDQ
GND
DQd
DQd
DQd
DQd
GND
VDDQ
DQd
DQd
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
69
12
68
13
67
14
66
15
65
16
64
17
63
18
62
19
61
20
60
21
59
22
58
23
57
24
56
25
55
26
54
27
53
28
52
29
51
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE
A
A
A
A
A1
A0
NC
NC
GND
VDD
NC
NC
A
A
A
A
A
A
A
DQPb
DQb
DQb
VDDQ
GND
DQb
DQb
DQb
DQb
GND
VDDQ
DQb
DQb
GND
NC
VDD
ZZ
DQa
DQa
VDDQ
GND
DQa
DQa
DQa
DQa
GND
VDDQ
DQa
DQa
DQPa
128K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW
CE, CE2,
CE2
OE
DQa-DQd
MODE
V
DD
GND
V
DDQ
ZZ
DQPa-DQPd
Synchronous Global Write Enable
Synchronous Chip Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V or
2.5V
Snooze Enable
Parity Data I/O
A
CLK
ADSP
ADSC
ADV
BW1-BW4
BWE
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
01/20/03
IS64LP12832
IS64LP12836, IS64LP25618
PIN CONFIGURATION
119-pin PBGA (Top View)
1
A
VDDQ
B
NC
C
NC
D
DQb
E
NC
F
VDDQ
G
NC
H
DQb
J
VDDQ
K
NC
L
DQb
M
VDDQ
N
DQb
P
NC
R
NC
T
NC
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
A
A
NC
A
A
ZZ
A
MODE
VDD
GND
A
NC
DQPb
GND
A0
GND
NC
DQa
NC
GND
A1
GND
DQa
NC
DQb
GND
NC
GND
NC
BWE
DQb
GND
CLK
GND
BW1
GND
NC
DQa
NC
DQa
NC
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
NC
GND
DQb
NC
GND
BW2
DQb
GND
NC
GND
NC
CE
OE
ADV
GW
GND
GND
GND
GND
GND
DQPa
NC
DQa
NC
DQa
NC
DQa
VDDQ
DQa
NC
7
A7
A2
2
VDD
A12
12
15
A15
NC
CE2
A3
3
A6
6
A4
4
2
3
4
5
6
7
ISSI
100-Pin TQFP
A
A
CE
CE2
NC
NC
BW2
BW1
CE2
VDD
GND
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
®
ADSP
ADSC
A8
8
A9
9
A16
16
CE2
VDDQ
NC
NC
NC
NC
VDDQ
GND
NC
NC
DQb
DQb
GND
VDDQ
DQb
DQb
NC
VDD
NC
GND
DQb
DQb
VDDQ
GND
DQb
DQb
DQPb
NC
GND
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80
1
79
2
78
3
77
4
76
5
75
6
74
7
73
8
72
9
71
10
70
11
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
VDDQ
GND
NC
DQPa
DQa
DQa
GND
VDDQ
DQa
DQa
GND
NC
VDD
ZZ
DQa
DQa
VDDQ
GND
DQa
DQa
NC
NC
GND
VDDQ
NC
NC
NC
256K x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Synchronous Byte Write Enable
Synchronous Byte Write Enable
5
GW
OE
DQa-DQb
MODE
V
DD
GND
V
DDQ
ZZ
DQPa-DQPb
Synchronous Global Write Enable
Output Enable
Synchronous Data Input/Output
Burst Sequence Mode Selection
+3.3V Power Supply
Ground
Isolated Output Buffer Supply: +3.3V
Snooze Enable
Parity Data I/O
CE,
CE2,
CE2
Synchronous Chip Enable
A
CLK
ADSP
ADSC
ADV
BW1-BW2
BWE
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
01/20/03
MODE
A
A
A
A
A1
A0
NC
NC
GND
VDD
NC
NC
A
A
A
A
A
A
A
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