Disabled outputs programmable as HiZ or Active Low.
•
Offered in Tiny
GREEN/RoHS
compliant packages
o
6-pin DFN (2.0mmx1.3mmx0.6mm)
o
6-pin SC70 (2.3mmx2.25mmx1.0mm)
o
6-pin SOT23 (3.0mmx3.0mmx1.35mm)
•
Single 1.8V, 2.5V, or 3.3V ± 10% power supply
•
Operating temperature range from -40°C to 85°C
DESCRIPTION
The PL611s-17 is a low-cost general purpose
frequency synthesizer and a member of PhaseLink’s
PicoPLL
TM
Factory Programmable ‘Quick Turn Clock
(QTC)’ family. Designed to fit in a small SOT23,
SC70, or DFN package for high performance, low
power applications, the PL611s-17 accepts a low
frequency (>10KHz) Reference input and generates
up to 125MHz outputs with the best phase noise,
jitter performance, and power consumption for
handheld devices and notebook applications. In
addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(F
OUT
, F
REF
, F
REF
/2) output. Cascading the PL611s-
17 with other PicoPLL ICs can result in producing all
required system clocks with specific savings in board
space, power consumption, and cost.
PACKAGE PIN CONFIGURATION
OE, PDB,
FSEL, CLK1
VDD
FIN
LF
1
2
3
6
5
4
CLK0
GND
GND
CLK0
LF
SOT23-6L
SOT23-
23
mmx3 mmx1 35mm
mm)
(3.0mmx3.0mmx1.35mm)
3
2
PL611s-17
PL611s-17
PL611s-17
PL611s-17
1
6
5
4
FIN
OE, PDB,
FSEL, CLK1
VDD
PL611s-17
FIN
OE, PDB, FSEL, CLK1
VDD
1
2
3
6
5
4
LF
GND
CLK0
DFN-
DFN-6L
mmx1 mmx0 mm)
(2.0mmx1.3mmx0.6mm)
BLOCK DIAGRAM
Ref.
R-Counter
(7-bit)
M-Counter
(16-bit)
PL611s-17
SC70-6L
SC70-
70
mmx2 25mmx mm)
mmx1
(2.3mmx2.25mmx1.0mm)
FIN
Phase
Detector
Charge
Pump
F
VCO
= F
Ref
* (M/R)
VCO
Programmable
Function
F
Out
= F
VCO
P-Counter
(4-bit)
/2*P
CLK0
Programming
Logic
OE, PDB,
FSEL, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/04/07 Page 1
(Preliminary)
PL611s-17
1.8V-3.3V PicoPLL
TM
KHz to MHz Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F
OUT
= F
REF
* (M / R) /(2*P)
Where M=16 bit
R= 7 bit
P= 4 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths to
choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured as:
•
•
•
•
•
OE - input
FSEL - input
PDB - input
CLK1 – output
HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Name
VDD
SOT
Pin#
1
Pin #
SC70
Pin#
2
DFN
Pin#
3
Type
P
VDD connection.
Description
This programmable I/O pin can be configured as Output Enable (OE)
input, Power Down (PDB) input, Frequency Selector (FSEL) or CLK1
clock output. This pin has an internal 10M pull up resistor (OE, PDB &
FSEL Only).
OE, PDB,
FSEL, CLK1
2
1
2
I/O
The OE and PDB features can be programmed to allow the output
to float (Hi Z), or to operate in the ‘Active low’ mode.
State
0
1 (default)
OE
Disable CLK
Normal mode
PDB
Power Down Mode
Normal mode
FSEL
Frequency ‘2’
Frequency ‘1’
FIN
LF
GND
CLK0
3
4
5
6
3
4
5
6
1
6
5
4
I
I
P
O
Reference input pin.
Loop Filter input pin.
GND connection
Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/04/07 Page 2
(Preliminary)
PL611s-17
1.8V-3.3V PicoPLL
TM
KHz to MHz Programmable Clock
FUNCTIONAL DESCRIPTION
PL611s-17 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-17 accepts a reference clock input of 10kHz to 200MHz and is
capable of producing two outputs up to 125MHz. This flexible design allows the PL611s-17 to deliver any PLL
generated frequency, F
REF
(Ref Clk) frequency or F
REF
/(2*P) to CLK0 and/or CLK1. Some of the design features
of the PL611s-17 are mentioned below:
PLL Programming
The PLL in the PL611s-17 is fully programmable.
The PLL is equipped with an 7-bit input frequency
divider (R-Counter), and an 16-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 4-bit post VCO divider (P-
Counter). The output frequency is determined by
the following formula [F
OUT
= F
REF
* (M / R) / (2 * P) ].
Clock Output (CLK0)
CLK0 is the main clock output. The PL611s-17 can
also be programmed to provide a second clock
output, CLK1, on the programmable I/O pin (see
OE/PDB/FSEL/CLK1 pin description below). The
output of CLK0 can be configured as the PLL output
(F
VCO
/(2*P)), F
REF
(Ref Clk Frequency) output, or
F
REF
/(2*P) output. The output drive level can be
programmed to Low Drive (4mA), Standard Drive
(8mA) or High Drive (16mA). The maximum output
frequency is 125MHz.
Clock Output (CLK1)
The CLK1 feature allows the PL611s-17 to have an
additional clock output. This output can be
programmed to one of the following:
F
REF
- Reference ( Ref Clk ) Frequency
F
REF
/ 2
CLK0
CLK0 / 2
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to put
the PL611s-17 into “Sleep Mode”. When activated
(logic ‘0’), PDB ‘Disables the PLL, the oscillator
circuitry, counters, and all other active circuitry. In
Power Down mode the IC consumes <10 A of power.
The PDB pin incorporates a 10M pull up resistor
giving a default condition of logic “1”.
The PDB feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode.
Frequency Select (FSEL)
The Frequency Select (FSEL) feature allows the
PL611s-17 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 10M pull
up resistor giving a default condition of logic “1”.
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 10M pull up resistor
giving a default condition of logic “1”.
The OE feature can be programmed to allow the
output to float (Hi Z), or to operate in the ‘Active low’
mode.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/04/07 Page 3
(Preliminary)
PL611s-17
1.8V-3.3V PicoPLL
TM
KHz to MHz Programmable Clock
APPLICATION RECOMMENDATIONS FOR PL611s-17
PL611s-17 can accept a reference input >10kHz and produce a clock output in the MHz range, as shown in the
diagram ‘1’, below. Also, to save costs in consumer product system designs and for greater area optimization, it
is possible to use the XOUT of the RTC crystal (32.768KHz) as the reference input to the PL611s-17, as shown in
diagram ‘2’, below.
XIN
C1
REFIN
OE, PDB
FSEL, CLK1
1.8~3.3V
XIN
32.768
KHz
ASIC
1
2
3
6
5
4
Diagram ‘1’
Note: An AC Coupling Cap may be required if RTC Clock amplitude is too small.
GUIDELINES FOR EXTERNAL COMPONENT SELECTION
For the optimum performance, an accurate external loop filter capacitor must be selected. A general guideline for
selecting this component based on the input frequency is shown in the table below.
Input Frequency
3MHz ~ 200MHz
300KHz ~ 10MHz
30KHz ~ 1.0MHz
10KHz ~ 100KHz
Capacitor Value
1.0nF
1.0nF
4.7nF
47nF
The optimal way to choose the value is using the following formula:
C(nF) = 0.8 + M/280
Where C = Loop Filter Capacitor value (in nF)
M = M counter value. Provided by PhaseLink with device samples.
Notes:
* Find the closest commercially available value. Values in the E12 range with 5% tolerance are acceptable.
* With possible M-counter values between 1 and 65536, the capacitor value is expected in the range 820pF thru
220nF.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 01/04/07 Page 4
PL611s-17
LF
LFGND
MHZ CLK
(Any Frequency)
C2
XOUT
XOUT
REFIN
OE, PDB
FSEL, CLK1
1.8~3.3V
1
2
3
6
5
4
Diagram ‘2’
PL611s-17
L611s-17
LF
LFGND
MHZ CLK
(Any Frequency)
(Preliminary)
PL611s-17
1.8V-3.3V PicoPLL
TM
KHz to MHz Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature (Green package)
Data Retention @ 85°C
Storage Temperature
Ambient Operating Temperature*
T
S
10
-65
-40
150
85
SYMBOL
V
DD
V
I
V
O
MIN.
-0.5
-0.5
-0.5
MAX.
7
V
DD
+0.5
V
DD
+0.5
260
UNITS
V
V
V
°C
Year
°C
°C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
@ V
DD
=3.3V
Input (FIN) Frequency
@ V
DD
=2.5V
@ V
DD
=1.8V
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Internally AC/DC coupled (High Frequency)
Internally AC/DC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ V
DD
=3.3V
Output Frequency
@ V
DD
=2.5V
@ V
DD
=1.8V
Settling Time
Output Enable Time
Output Rise Time
Output Fall Time
Duty Cycle
Period Jitter, Pk-to-Pk*
(measured from 10,000 samples)
At power-up (after V
DD
increases over 1.62V)
OE Function; Ta=25º C, 15pF Load
PDB Function; Ta=25º C, 15pF Load
15pF Load, 10/90% V
DD
, High Drive, 3.3V
15pF Load, 90/10% V
DD
, High Drive, 3.3V
V
DD
/2
With capacitive decoupling between V
DD
and
GND.
45
1.2
1.2
50
70
0.9
0.1
10KHz
CONDITIONS
MIN.
TYP.
MAX.
200
166
133
V
DD
V
DD
125
90
65
2
10
2
1.7
1.7
55
UNITS
MHz
Vpp
V
pp
MHz
ms
ns
ms
ns
ns
%
ps
* Note: Jitter performance depends on the programming parameters.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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