CAT25C11/03/05/09/17
1K/2K/4K/8K/16K SPI Serial CMOS EEPROM
FEATURES
s
10 MHz SPI compatible
s
1.8 to 6.0 volt operation
s
Hardware and software protection
s
Low power CMOS technology
s
SPI modes (0,0 & 1,1)*
s
Commercial, industrial, automotive and extended
s
1,000,000 program/erase cycles
s
100 year data retention
s
Self-timed write cycle
s
8-pin DIP/SOIC, 8-pin TSSOP and 8-pin MSOP
s
16/32-byte page write buffer
s
Write protection
temperature ranges
– Protect first page, last page, any 1/4 array or
lower 1/2 array
DESCRIPTION
The CAT25C11/03/05/09/17 is a 1K/2K/4K/8K/16K-Bit
SPI Serial CMOS EEPROM internally organized as
128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s
advanced CMOS Technology substantially reduces
device power requirements. The CAT25C11/03/05
features a 16-byte page write buffer. The 25C09/17
features a 32-byte page write buffer.The device operates
via the SPI bus serial interface and is enabled though a
Chip Select (CS). In addition to the Chip Select, the clock
PIN CONFIGURATION
CS
SO
WP
VSS
MSOP Package (R, Z, GZ)* SOIC Package (S, V, GV)
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
*CAT25C11/03 only
PIN FUNCTIONS
Pin Name
SO
SCK
WP
V
CC
V
SS
CS
SI
i
D
c
s
Ground
Function
Serial Data Output
u
n
i
t
n
o
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
input (SCK), data in (SI) and data out (SO) are required
to access the device. The
HOLD
pin may be used to
suspend any serial communication without resetting the
serial sequence. The CAT25C11/03/05/09/17 is designed
with software and hardware write protection features
including Block Write protection. The device is available
in 8-pin DIP, 8-pin SOIC, 8/14-pin TSSOP and 8-pin
MSOP packages.
d
e
8
7
6
5
VCC
HOLD
SCK
SI
a
P
CS
SO
WP
VSS
1
2
3
4
s
t
r
8
7
6
5
VCC
HOLD
SCK
SI
DIP Package (P, L, GL)
CS
SO
WP
VSS
1
2
3
4
TSSOP Package (U, Y, GY)
BLOCK DIAGRAM
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
Serial Clock
Write Protect
+1.8V to +6.0V Power Supply
SO
SI
CS
WP
HOLD
SCK
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
CONTROL LOGIC
XDEC
EEPROM
ARRAY
Chip Select
Serial Data Input
Suspends Serial Input
No Connect
HOLD
NC
DATA IN
STORAGE
HIGH VOLTAGE/
TIMING CONTROL
* Other SPI modes available on request.
STATUS
REGISTER
Doc. No. 1017, Rev. L
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
CAT25C11/03/05/09/17
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
SS(1)
.................. –2.0V to +V
CC
+2.0V
V
CC
with Respect to V
SS ................................
–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Typ.
Max.
1,000,000
100
2000
100
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB(6)
I
LI
I
LO
V
IL(5)
V
OL1
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby)
Input Leakage Current
Output Leakage Current
Input Low Voltage
V
IH(5)
V
OH1
V
OL2
V
OH2
i
D
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
V
CC
-0.2
V
CC
- 0.8
c
s
u
n
i
t
n
o
Limits
Typ.
Min.
-1
V
CC
x 0.7
Max.
5
3
1
2
3
d
e
0.4
a
P
Cycles/Byte
Years
Volts
mA
s
t
r
Units
Units
mA
mA
µA
µA
µA
V
V
V
V
Test Conditions
V
CC
= 5V @ 5MHz
SO=open; CS=Vss
V
CC
= 5.5V
F
CLK
= 5MHz
CS
= V
CC
V
IN
= V
SS
or V
CC
V
OUT
= 0V to V
CC
,
CS = 0V
V
CC
x 0.3
V
CC
+ 0.5
2.7V≤V
CC
<5.5V
I
OL
= 3.0mA
I
OH
= -1.6mA
1.8V≤V
CC
<2.7V
I
OL
= 150µA
I
OH
= -100µA
0.2
V
V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) V
ILMIN
and V
IHMAX
are reference values only and are not tested.
(6) Maximum standby current (I
SB
) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1017, Rev. L
2
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C11/03/05/09/17
PIN CAPACITANCE
(1)
Applicable over recommended operating range from T
A
=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
C
OUT
C
IN
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI,
WP, HOLD)
Max.
8
6
Units
pF
pF
Conditions
V
OUT
=0V
V
IN
=0V
A.C. CHARACTERISTICS
Limits
1.8V-6.0V
SYMBOL PARAMETER
t
SU
t
H
t
WH
t
WL
f
SCK
t
LZ
t
RI(1)
t
FI(1)
t
HD
t
CD
t
WC(3)
t
V
t
HO
t
DIS
t
HZ
t
CS
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
HOLD
to Output Low Z
Input Rise Time
Input Fall Time
Min.
50
50
250
250
DC
1
50
2
2.5V-6.0V
Max.
20
20
75
75
DC
4.5V-5.5V
Min.
20
20
Max. Min.
Max.
HOLD
Setup Time
HOLD
Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD
to Output High Z
CS
High Time
t
CSS
t
CSH
t
WPS
t
CSH
(1)
(2)
i
D
CS
Setup Time
CS
Hold Time
WP
Setup Time
CS
Hold Time
(3)
This parameter is tested initially and after a design or process change that affects the parameter.
AC Test Conditions:
Input Pulse Voltages: 0.3V
CC
to 0.7V
CC
Input rise and fall times:
≤10ns
Input and output reference voltages: 0.5V
CC
Output load: current source IOL max/IOH max; C
L
= 50pF
t
WC
is the time from the rising edge of
CS
after a valid write sequence to the end of the internal write cycle.
c
s
u
n
i
t
n
o
2
100
40
100
40
10
250
0
0
250
150
500
100
500
100
500
100
50
50
150
150
d
e
40
5
DC
50
2
2
40
40
5
75
0
75
50
100
100
100
50
50
40
10
50
2
2
a
P
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
5
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNITS Conditions
V
IH
= 2.4V
s
t
r
Test
C
L
= 100pF
V
OL
= 0.8V
V
OH
= 2.0v
C
L
= 50pF
(note 2)
C
L
= 100pF
40
75
50
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 1017, Rev. L
CAT25C11/03/05/09/17
FUNCTIONAL DESCRIPTION
The CAT25C11/03/05/09/17 supports the SPI bus data
transmission protocol. The synchronous Serial Periph-
eral Interface (SPI) helps the CAT25C11/03/05/09/17 to
interface directly with many of today’s popular
microcontrollers. The CAT25C11/03/05/09/17 contains
an 8-bit instruction register. (The instruction set and the
operation codes are detailed in the instruction set table)
After the device is selected with
CS
going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
Figure 1. Sychronous Data Timing
the operation to be performed.
PIN DESCRIPTION
SI:
Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C11/03/05/09/17.Input data is latched on the rising
edge of the serial clock for SPI modes (0, 0 & 1, 1).
SO:
Serial Output
SO is the serial data output pin. This pin is used to transfer
data out of the 25C11/03/05/09/17. During a read cycle,
data is shifted out on the falling edge of the serial clock for
CS
SO
NC
NC
NC
NC
WP
V
SS
INSTRUCTION SET
Instruction
WREN
WRDI
Note: Dashed Line= mode (1, 1) – – – –
RDSR
WRSR
READ
WRITE
Power-Up Timing
(2)(3)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
i
D
c
s
0000 0110
0000 0100
0000 0101
u
n
i
t
n
o
Opcode
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
d
e
HOLD
NC
NC
NC
a
P
s
t
r
NC
SCK
SI
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
0000 0001
0000 X011
(1)
0000 X010
(1)
Note:
(1) X=0 for 25C11, 25C03, 25C09, 25C17. X=A8 for 25C05
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Doc. No. 1017, Rev. L
4
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25C11/03/05/09/17
and forces the devices into a Standby Mode (unless an
internal write operation is underway) The CAT25C11/03/
05/09/17 draws ZERO current in the Standby mode. A
high to low transition on
CS
is required prior to any
sequence being initiated. A low to high transition on
CS
after a valid write sequence is what initiates an internal
write cycle.
WP
Write Protect
WP:
WP
is the Write Protect pin. The Write Protect pin will allow
normal read/write operations when held high. When
WP
is
tied low and the WPEN bit in the status register is set to "1",
all write operations to the status register are inhibited.
WP
going low while
CS
is still low will interrupt a write to the
status register. If the internal write cycle as already been
initiated,
WP
going low will have no effect on any write
Address Don't Care Bits
A7
SPI modes (0,0 & 1,1).
SCK:
Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
25C11/03/05/09/17. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge of
the SCK for SPI modes (0,0 & 1,1).
CS:
CS
Chip Select
CS
is the Chip select pin.
CS
low enables the CAT25C11/
03/05/09/17 and
CS
high disables the CAT25C11/03/05/
09/17.
CS
high takes the SO output pin to high impedance
BYTE ADDRESS
Device
CAT25C11
CAT25C03
CAT25C05
CAT25C09
CAT25C17
STATUS REGISTER
7
WPEN
6
1
Address Significant Bits
A6 - A0
A7 - A0
A7 - A0 (A8 = X bit from Opcode)
A9 - A0
A10 - A0
A15 - A10
A15 - A11
MEMORY PROTECTION
BP2
0
0
0
0
1
1
1
1
BP1
0
0
1
1
0
0
1
1
BP0
0
1
0
1
0
1
0
1
WRITE PROTECT ENABLE OPERATION
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
Protected
Blocks
Protected
Protected
Protected
Protected
Protected
Protected
5
i
D
c
s
u
n
i
t
n
o
5
4
3
1
BP2
BP1
Non-Protection
Q1 Protected
Q2 Protected
Q3 Protected
Q4 Protected
H1 Protected
P0 Protected
Pn Protected
Q1
Q2
Q3
Q4
H1
P0
Pn
d
e
—
—
2
BP0
25C03
00-3F
40-7F
80-BF
C0-FF
00-7F
00-0F
F0-FF
a
P
8
8
8
1
WEL
# Address Clock Pulse
s
t
r
0
RDY
25C17
000-1FF
200-3FF
400-5FF
600-7FF
000-3FF
000-01F
7E0-7FF
16
16
25C11
00-1F
20-3F
40-5F
60-7F
00-3F
25C05
000-07F
080-0FF
100-17F
180-1FF
000-0FF
000-00F
25C09
000-0FF
100-1FF
200-2FF
300-3FF
000-1FF
000-01F
00-0F
70-7F
1F0-1FF 3E0-3FF
Unprotected
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status
Register
Protected
Writable
Protected
Protected
Protected
Writable
Doc. No. 1017, Rev. L
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
