Rev. 1.2
32M Bits Serial Pseudo-SRAM with SPI and QPI
LY68S3200
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Description
Initial Issued
Added
POWER UP INITIALIZATION
in page2
&
COMMAND TERMINATION
in page3
Revised
QPI Mode : Write Operations(38h or 02h)
in page8
Revised Operating Temperature to (-25℃ to 85℃)
Issue Date
Sep.8. 2015
Dec.15. 2015
Dec.25. 2015
2F, No. 17, lndustry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan
TEL: 886-3-6668838
FAX: 886-3-6668836
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
0
Rev. 1.2
32M Bits Serial Pseudo-SRAM with SPI and QPI
GENERAL DESCRIPTION
LY68S3200
FEATURES
SPI compatible bus interface
- Clock rate:
33MHz(max) for normal read
100MHz(max) for fast read
- Mode: SPI/QPI
Low power consumption:
Operating current: 20mA(TYP.)
Single 1.8V power supply
Unlimited read/write cycle
Fast write time as minimum cycle time
4M x 8-bit organization
-
1K byte per page
High Reliability
Green package available
Package : 8-pin 150 mil SOP
The LY68S3200 is a 32M-bit serial pseudo SRAM
device organized as 4Mx8 bits. It is fabricated using
very high performance, high reliability CMOS
technology.
The LY68S3200 is accessed via a simple Serial
Peripheral Interface(SPI) compatible serial bus.
Additionally, Quad Peripheral Interface(QPI) is
supported if your application needs faster data rates.
This device also supports unlimited reads and writes
to the memory array.
The LY68S3200 operates from a single power
supply of 1.8V and can offer high data bandwidth at
100MHz clock rate and Serial Quad interface.
The LY68S3200 offers 8-lead SOP package.
Pin Configuration
PIN DESCRIPTION
SYMBOL
SI/SIOI[0]
SO/SIO[1]
SIO[2]
SIO[3]
CE#
SCLK
V
CC
V
SS
SPI MODE
Serial Input
Serial Output
-
-
Chip Select Input
Clock Signal Input
Power Supply
Ground
SQI MODE
Serial I/O[0]
Serial I/O[1]
Serial I/O[2]
Serial I/O[3]
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
Voltage on V
CC
relative to V
SS
Voltage on any other pin relative to V
SS
Operating Temperature
Storage Temperature
SYMBOL
V
T1
V
T2
T
A
T
STG
RATING
-0.5 to 2.3
-0.5 to V
CC
+0.5
-25 to 85
-65 to 150
UNIT
V
V
℃
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
2F, No. 17, lndustry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan
TEL: 886-3-6668838
FAX: 886-3-6668836
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
1
Rev. 1.2
32M Bits Serial Pseudo-SRAM with SPI and QPI
LY68S3200
POWER-UP INITIALIZATION
The LY68S3200 includes an on-chip voltage sensor used to start the self-initialization process. When V
CC
reaches a stable level at or above minimum V
CC
, the device will require 150µs to complete its self-initialization
process. From the beginning of power ramp to the end of the 150µs period, SCLK should remain LOW, CE#
should remain HIGH(track V
CC
within 200mV) and SI/SO/SIO[3:0] should remain LOW.
After the 150µs period, the device requires at least one clock during CE# high to properly reset the device,
and then the device is ready for normal opearion.
Command/Address Latching Truth Table
SPI Mode
Wait
DIO
Addr
Cycle
S
0
S
S
8
S
Q
6
Q
S
0
S
Q
0
Q
-
-
-
N/A
Max
Freq.
33
100
100
100
100
100
QPI Mode
Wait
Addr
Cycle
N/A
N/A
Q
6
Q
0
Q
0
N/A
-
-
Max
Freq.
100
100
100
100
Command
Read
Fast Read
Quad Read
Write
Quad Write
Enter QPI Mode
Exit QPI Mode
Code
03h
0Bh
EBh
02h
38h
35h
F5h
Cmd
S
S
S
S
S
S
Cmd
DIO
Q
Q
Q
Q
Q
Q
Q
-
Note: S = Serial IO, Q = Quad IO
2F, No. 17, lndustry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan
TEL: 886-3-6668838
FAX: 886-3-6668836
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
2
Rev. 1.2
32M Bits Serial Pseudo-SRAM with SPI and QPI
LY68S3200
COMMAND TERMINATION
All Reads & Writes must be completed by a clock pulse of CE# high immediately afterwards in order to
terminate the active read/write wordline and set the device into standby. Not doing so will block internal refresh
operations until the device sees the read/write wordline terminated.
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
MIN.
PARAMETER
Supply Voltage
V
CC
1.65
Input High Voltage
V
IH
Vcc-0.4
Input Low Voltage
V
IL
- 0.2
Input Leakage Current
I
LI
V
CC
≧
V
IN
≧
V
SS
-1
Output Leakage
V
CC
≧
V
OUT
≧
V
SS
,
I
LO
-1
Current
Output Disabled
Output High Voltage
V
OH
I
OH
= -0.2mA
0.8*Vcc
Output Low Voltage
V
OL
I
OL
= +0.2mA
-
CE#
≦
0.2,
SPI@33MHz
-
Average Operating
Others at 0.2V
I
CC1
Power Supply Current
or Vcc-0.2V
QPI@100MHz
-
I
I/O
= 0mA;f=max
Standby Power
CE#
≧
V
CC
- 0.2V,
I
SB1
-
Supply Current
Others at 0.2V or V
CC
- 0.2V
Notes:
1. Typical values are included for reference only and are not guaranteed or tested.
Typical valued are measured at V
CC
= V
CC
(TYP.) and T
A
= 25℃
MAX.
TYP.
*1
1.8
1.95
-
V
CC
+0.2
-
0.4
-
1
-
-
-
6
20
-
1
-
0.2*Vcc
15
30
150
UNIT
V
V
V
µA
µA
V
V
mA
mA
µA
2F, No. 17, lndustry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan
TEL: 886-3-6668838
FAX: 886-3-6668836
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
3
Rev. 1.2
32M Bits Serial Pseudo-SRAM with SPI and QPI
LY68S3200
CAPACITANCE
(T
A
= 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN.
-
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to Vcc-0.2V
1.5ns
V
CC
/2
C
L
= 30pF + 1TTL, I
OH
/I
OL
= -0.2mA/+0.2mA
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Clock Cycle Time
Clock low width
Clock high width
Clock rise time
Clock fall time
CE# setup time to CLK rising edge
Setup time to active CLK edge
Hold time from active CLK edge
Chip disable to DQ output high-Z
CLK falling to output valid
Output Hold from Clock falling
CE# low pulse width
SYM.
t
CLK@33MHz
t
CLK@100MHz
t
CL
t
CH
t
R
t
F
t
CSP
t
S
t
H
t
HZ
t
ACLK
t
OH
t
CEM
LY68S3200
MIN.
MAX.
30
-
10
-
0.45
0.55
0.45
0.55
-
1.5
-
1.5
2.5
-
2.5
-
2
-
-
7
-
7
1.5
-
-
5
UNIT
ns
ns
t
CLK
t
CLK
ns
ns
ns
ns
ns
ns
ns
ns
us
2F, No. 17, lndustry E. Rd. II, Science-Based Industrial Park, Hsinchu 300, Taiwan
TEL: 886-3-6668838
FAX: 886-3-6668836
Lyontek Inc.
reserves the rights to change the specifications and products without notice.
4
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