IMP705/6/7/8, 8 13L
P
OWER
M
ANAGEMENT
Low-Power µP Supervisor Circuits
–
–
–
Watc hdog timer
Br o wnout det ection
Po w er suppl y monit or
Key Features
N
Improved replacements for the Maxim
MAX705/6/7/8, MAX813L
– 140µA maximum supply current
– 60% improvement
N
Precision power supply monitor
– 4.65V threshold (IMP705/707/813L)
– 4.40V threshold (IMP706/8)
N
Debounced manual reset input
N
Voltage monitor
– 1.25V threshold
– Battery monitor/Auxiliary supply monitor
N
Watchdog timer (IMP705/706/813L)
N
200ms reset pulse width
N
Active HIGH reset output (IMP707/708/813L)
N
MicroSO package
The IMP705/706/707/708 and IMP813L CMOS supervisor circuits
monitor power-supply and battery voltage level, and
µP/µC
operation.
Compared to pin-compatible devices offered by Maxim Integrated
Products, IMP devices feature 60 percent lower maximum supply current.
The family offers several functional options. Each device generates a
reset signal during power-up, power-down and during brownout
conditions. A reset is generated when the supply drops below
4.65V (IMP705/707/813L) or 4.40V (IMP706/708). For 3V power supply
applications, refer to the IMP705P/R/S/T data sheet. In addition, the
IMP705/706/813L feature a 1.6 second watchdog timer. The IMP707/708
have both active-HIGH and active-LOW reset outputs but no watchdog
function. The IMP813L has the same pin-out and functions as the IMP705
but has an active-HIGH reset output. A versatile power-fail circuit has a
1.25V threshold, useful in checking battery levels and non-5V supplies. All
devices have a manual reset (MR) input. The watchdog timer output will
trigger a reset if connected to MR.
All devices are available in 8-pin DIP, SO and MicroSO packages.
Applications
N
N
N
N
N
Computers and embedded controllers
Battery-operated systems
Intelligent instruments
Wireless communication systems
PDAs and handheld equipment
Block Diagrams
WDI
V
CC
Transition
Detector
Watchdog
Timer
WDO
RESET
V
CC
0.25mA
Timebase
0.25mA
MR
V
CC
+
+
–
RESET
Generator
RESET
(RESET)
(IMP813L)
MR
V
CC
+
+
–
4.65V (IMP707)
4.40V (IMP708)
RESET
Generator
RESET
4.65V (IMP705/813L)
4.40V (IMP706)
PFI
+
IMP705
IMP706
IMP813L
1.25V
–
PFO
PFI
1.25V
+
PFO
–
IMP707
IMP708
GND
705_01.eps
705_02.eps
GND
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Daily Silver IMP
1
IMP705/6/7/8, 8 13L
Pin Configuration
DIP/SO
MR
V
CC
GND
PFI
1
2
3
4
IMP707
IMP708
8
7
6
5
RESET
RESET
NC
PFO
MR
V
CC
GND
PFI
1
2
3
4
IMP705
IMP706
(IMP813L)
8
7
6
5
WDO
RESET (RESET)
WDI
PFO
RESET
RESET
MR
V
CC
1
2
3
4
IMP707
IMP708
8
7
6
5
MicroSO
NC
PFO
PFI
GND
RESET (RESET)
WDO
MR
V
CC
1
2
3
4
IMP705
IMP706
(IMP813L)
8
7
6
5
WDI
PFO
PFI
GND
705_03.eps
Ordering Information
Part Number
Reset Threshold (V)
Temperature Range
IMP705 Active LOW Reset, Watchdog Output and Manual RESET
IMP705CPA
IMP705CSA
IMP705CUA
IMP705C/D
IMP705EPA
IMP705ESA
IMP706ESA
IMP706CPA
IMP706CSA
IMP706CUA
IMP706C/D
IMP706EPA
IMP706ESA
IMP707CPA
IMP707CSA
IMP707CUA
IMP707C/D
IMP707EPA
IMP707ESA
IMP708CPA
IMP708CSA
IMP708CUA
IMP708C/D
IMP708EPA
IMP708ESA
IMP813LCPA
IMP813LCSA
IMP813LCUA
IMP813LC/D
IMP813LEPA
IMP813LESA
4.65
4.65
4.65
4.65
4.65
4.65
4.40
4.40
4.40
4.40
4.40
4.40
4.40
4.65
4.65
4.65
4.65
4.65
4.65
4.40
4.40
4.40
4.40
4.40
4.40
4.65
4.65
4.65
4.65
4.65
4.65
0°C to +70°C
0°C to +70°C
0°C to +70°C
25°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
25°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
25°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
25°C
–40°C to +85°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
25°C
–40°C to +85°C
–40°C to +85°C
Pins-Package
8-Plastic DIP
8-SO
8-MicroSO
Dice
8-Plastic DIP
8-SO
8-SO
8-Plastic DIP
8-SO
8-MicroSO
Dice
8-Plastic DIP
8-SO
8-Plastic DIP
8-SO
8-MicroSO
Dice
8-Plastic DIP
8-SO
8-Plastic DIP
8-SO
8-MicroSO
Dice
8-Plastic DIP
8-SO
8-Plastic DIP
8-SO
8-MicroSO
Dice
8-Plastic DIP
8-SO
IMP706 Active LOW Reset, Watchdog Output and Manual RESET
IMP707 Active LOW & HIGH Reset with Manual RESET
IMP708 Active LOW & HIGH Reset with Manual RESET
IMP813L Active HIGH Reset, Watchdog Output and Manual RESET
2
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Daily Silver IMP
IMP705/6/7/8, 8 13L
Absolute Maximum Ratings
Pin Terminal Voltage with Respect to Ground
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 6.0V
All other inputs
1
. . . . . . . . . . . . . . . . . . . . . . . . –0.3V to (V
CC
+ 0.3V)
Input Current at V
CC
and GND . . . . . . . . . . 20mA
Output Current: All outputs . . . . . . . . . . . . . 20mA
Rate of Rise at V
CC
. . . . . . . . . . . . . . . . . . . . . 100V/µs
Plastic DIP Power Dissipation . . . . . . . . . . . 700 mW
(Derate 9 mW/°C above 70°C)
SO Power Dissipation . . . . . . . . . . . . . . . . . 470 mW
(Derate 5.9 mW/°C above 70°C)
MicroSO Power Dissipation . . . . . . . . . . . . . 330mW
(Derate 4.1 mW/°C above 70°C)
Operating Temperature Range
IMP705E/706E/707E/708E/813LE . . . . . . . –40°C to 85°C
IMP706C/707C/708C/813LC . . . . . . . . . . . 0°C to 70°C
Storage Temperature Range . . . . . . . . . . . . . . –65°C to 160°C
Lead Temperature Soldering(10 sec) . . . . . . 300°C
Note: 1. The input voltage limits on PFI and MR can be exceeded if
the input current is less than 10mA.
These are stress ratings only and functional operation is not implied.
Electrical Characteristics
Unless otherwise noted, V
CC
= 4.75V to 5.5V for the IMP705/707/813L. V
CC
= 4.5V to 5.5V for the IMP706/708 and over the
operating temperature range.
Parameter
Operating Voltage Range
Symbol
V
CC
Conditions
IMP705/6/7/8C
IMP813L
IMP705/6/7/8E, IMP813lE
IMP705C/706C/813LC
IMP705E, IMP706E, IMP813LE
IMP707C, IMP708C
IMP707E, IMP708E
IMP705, IMP707, IMP813L, Note 2
IMP706, IMP708, Note 2
Note 2
Note 2
Note 2
Min
1.2
1.1
1.2
Typ
Max
5.5
5.5
5.5
140
140
140
140
4.75
4.50
280
0.25
Units
V
Supply Current
I
CC
RESET Threshold
RESET Threshold Hysteresis
RESET Pulse Width
MR Pulse Width
MR to RESET Out Delay
MR Input Threshold
MR Pull-up Current
RESET Output Voltage
V
RT
4.50
4.25
140
0.15
2.0
t
RS
t
MR
t
MD
V
IH
V
IL
75
75
50
50
4.65
4.40
40
200
µA
V
mV
ms
µs
µs
V
µA
V
RESET Output Voltage
Watchdog Timeout Period
WDI Pulse Width
WDI Input Threshold
WDI Input Current
WDO Output Voltage
PFI Input Threshold
PFI Input Current
PFO Output Voltage
t
WD
t
WP
V
IH
V
IL
MR = 0V
I
SOURCE
= 800µA
I
SINK
= 3.2mA
IMP705/6/7/8, V
CC
= 1.2V, I
SINK
= 100µA
IMP707/708/813L, I
SOURCE
= 800µA
IMP707/708, I
SINK
= 1.2mA
IMP813L, I
SINK
= 3.2mA
IMP813L, V
CC
=1.2V, I
SOURCE
= 4µA
IMP705/706/813L
V
IL
= 0.4V, V
IH
= 0.8V
CC
IMP705/706/813L, V
CC
= 5V
IMP705/706/813L, WDI = V
CC
IMP705/706/813L, WDI = 0V
IMP705/706/813L, I
SOURCE
= 800µA
IMP705/706/813L, I
SINK
= 1.2mA
V
CC
= 5V
I
SOURCE
= 800µA
I
SINK
= 3.2mA
100
V
CC
- 1.5V
250
0.8
600
0.4
0.3
V
CC
- 1.5V
0.4
0.4
0.9
1.00
50
3.5
1.60
2.25
V
s
ns
V
µA
V
–150
V
CC
- 1.5V
1.2
– 25
V
CC
- 1.5V
50
– 50
0.8
150
1.25
0.01
0.4
1.3
25
0.4
V
nA
V
Notes: 2. RESET (IMP705/6/7/8), RESET (IMP707/8, IMP813L)
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IMP705/6/7/8, 8 13L
Pin Descriptions
Pin Number
IMP705/706
IMP707/708
IMP813L
DIP/SO MicroSO DIP/SO MicroSO DIP/SO MicroSO Name
1
2
3
4
5
3
4
5
6
7
1
2
3
4
5
3
4
5
6
7
1
2
3
4
5
3
4
5
6
7
MR
V
CC
GND
PFI
PFO
Function
Manual RESET input. The active LOW input triggers a reset
pulse. A 250µA pull-up current allows the pin to be driven
by TTL / CMOS logic or shorted to ground with a switch.
+5V power supply input.
Ground reference for all signals.
Power-fail voltage monitor input. With PFI less than
1.25V, PFO goes low. Connect PFI to ground or V
CC
when not used.
Power-fail output. The output is active LOW and sinks
current when PFI is less than 1.25V.
Watchdog input. WDI controls the internal watchdog
timer. A HIGH or LOW signal for 1.6sec at WDI
allows the internal timer to run-out, setting WDO LOW.
The watchdog function is disabled by floating WDI or
by connecting WDI to a high-impedance three-state
buffer. The internal watchdog timer clears when:
RESET is asserted; WDI is three-stated; or WDI sees
a rising or falling edge.
Not connected.
Active-LOW reset output. Pulses LOW for 200ms
when triggered, and stays low whenever V
CC
is below
the reset threshold (IMP705: 4.65V, IMP705J: 4.00V,
IMP706: 4.40V). RESET remains LOW for 200ms
after V
CC
rises above the RESET threshold or MR
goes from LOW to HIGH. A watchdog timeout will not
trigger RESET unless WDO is connected to MR.
Watchdog output. WDO pulls LOW when the 1.6 sec
internal watchdog timer times-out and does not go
HIGH until the watchdog is cleared. In addition, when
V
CC
is below the reset threshold, WDO remains low.
Unlike RESET, WDO does not have a minimum pulse
width and as soon as V
CC
exceeds the reset
threshold, WDO goes HIGH with no delay.
Active-HIGH reset output. RESET is the inverse of
RESET. The IMP813L has only a RESET output.
6
8
—
—
6
8
WDI
—
—
6
—
—
—
NC
7
1
7
1
—
—
RESET
8
2
—
—
8
2
WDO
—
—
8
2
7
1
RESET
Feature Summary
IMP705
Power-fail detector
Brownout detection
Manual RESET input
Power-up/down RESET
Watchdog timer
Active-HIGH RESET output
Active-LOW RESET output
RESET threshold
4
IMP706
I
I
I
I
I
I
4.40V
IMP707
I
I
I
I
I
I
4.65V
IMP708
I
I
I
I
I
I
4.40V
IMP813L
I
I
I
I
I
I
4.65V
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I
I
I
I
I
I
4.65V/4.00V
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IMP705/6/7/8, 8 13L
Detail Descriptions
RESET/RESET Operation
The RESET/RESET signals are designed to start a
µP/µC
in a
known state or return the system to a known state.
The IMP707/708 have two RESET outputs, one active-HIGH
RESET and one active-LOW RESET output. The IMP813L has
only an active-HIGH output. RESET is simply the complement
of RESET.
RESET is guaranteed to be LOW with V
CC
above 1.2V. During a
power-up sequence, RESET remains low until the supply rises
above the threshold level, either 4.65V, 4.40V or 4.00V. RESET goes
.
high approximately 200ms after crossing the threshold.
During power-down, RESET goes LOW as V
CC
falls below the
threshold level and is guaranteed to be under 0.4V with V
CC
above 1.2V.
In a brownout situation where V
CC
falls below the threshold
level, RESET pulses low. If a brownout occurs during an already-
initiated reset, the pulse will continue for a minimum of 140ms.
Manual Reset (MR)
The active-LOW manual reset input is pulled high by a 250µA
pull-up current and can be driven low by CMOS/TTL logic or a
mechanical switch to ground. An external debounce circuit is
unnecessary since the 140ms minimum reset time will debounce
mechanical pushbutton switches.
By connecting the watchdog output (WDO) and MR, a watchdog
timeout forces RESET to be generated. The IMP813L should be
used when an active-HIGH RESET is required.
Watchdog Timer
The watchdog timer available on the IMP705/706/813L monitors
µP/µC
activity. If activity is not detected within 1.6 seconds, the
internal timer puts the watchdog output, WDO, into a LOW
state. WDO will remain LOW until activity is detected at WDI.
The watchdog function is disabled, meaning it is cleared and not
counting, if WDI is floated or connected to a three-stated circuit.
The watchdog timer is also disabled if RESET is asserted. When
RESET becomes inactive and the WDI input sees a high or low
transition as short as 50ns, the watchdog timer will begin a 1.6
second countdown. Additional transitions at WDI will reset the
watchdog timer and initiate a new countdown sequence.
WDO will also become LOW and remain so, whenever the
supply voltage, V
CC
, falls below the device threshold level. WDO
goes HIGH as soon as V
CC
transitions above the threshold. There
is no minimum pulse width for WDO as there is for the RESET
outputs. If WDI is floated, WDO essentially acts as a low-power
output indicator.
Auxiliary Comparator
All devices have an auxiliary comparator with 1.25V trip point
and uncommitted output (PFO) and noninverting input (PFI).
This comparator can be used as a supply voltage monitor with an
external resistor voltage divider. The attenuated voltage at PFI
should be set just below the 1.25 threshold. As the supply level
falls, PFI is reduced causing the PFO output to transit LOW.
Normally PFO interrupts the processor so the system can be shut
down in a controlled manner.
5V
V
CC
0V
v
RT
t
RS
t
RS
5V
WDI
0V
t
WD
t
WP
t
WD
5V
5V
RESET
0V
WDO
0V
t
WD
5V
5V
MR extermally
set low
t
MD
t
MR
MR
0V
RESET
0V
RESET triggered by MR
t
RS
5V
WDO
0V
705_04.eps
(RESET)
IMP813L
0V
705_05.eps
5V
Figure 1. WDI Three-state operation
Figure 2. Watchdog Timing
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