®
SG3524
REGULATING PULSE WIDTH MODULATORS
COMPLETE PWM POWER CONTROL CIR-
CUITRY
UNCOMMITTED OUTPUTS FOR SINGLE-
ENDED OR PUSH PULL APPLICATIONS
LOW STANDBY CURRENT 8mA TYPICAL
OPERATION UP TO 300KHz
1% MAXIMUM TEMPERATURE VARIATION
OF REFERENCE VOLTAGE
DESCRIPTION
The SG3524 incorporates on a single monolithic
chip all the function required for the construction
of regulating power suppies inverters or switching
regulators. They can also be used as the control
element for high power-output applications. The
SG3524 family was designed for switching regu-
lators of either polarity, transformer-coupled dc-
to-dc converters, transformerless voltage dou-
blers and polarity converter applications
employing fixed-frequency, pulse-width modula-
tion techniques. The dual alternating outputs al-
lows either single-ended or push-pull applications.
BLOCK DIAGRAM
DIP16
SO16
ORDERING NUMBERS:
SG3524N (DIP16)
SG3524P (SO16)
Each device includes an on-ship reference, error
amplifier, programmable oscillator, pulse-steering
flip flop, two uncommitted output transistors, a
high-gain comparator, and current-limiting and
shut-down circuitry.
July 2000
1/9
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
SG3524
PRINCIPLES OF OPERATION
The SG3524 is a fixed frequency pulse-with-
modulation voltage regulator control circuit. The
regulator operates at a frequency that is pro-
grammed by one timing resistor (R
T
) and one tim-
ing capacitor (C
T
). R
T
established a constant
charging current for C
T
. This results in a linear
voltage ramp at C
T
, which is fed to the compara-
tor providing linear control of the output pulse
width by the error amplifier. the SG3524 contains,
an on-board 5V regulator that serves as a refer-
ence as well as powering the SG3524’s internal
control circuitry and is also useful in supplying ex-
ternal support functions. This reference voltage is
lowered externally by a resistor divider to provide
a reference within the common mode range the
error amplifier or an external reference may be
used. The power supply output is sensed by a
second resistor divider network to generale a
feedback signal to error amplifier. The amplifier
output voltage is then compared to the linear volt-
age ramp at C
T
. The resulting modulated pulse
out of the high-gain comparator is then steered to
the appropriate output pass transistors (Q
A
or Q
B
)
by the pulse-steering flip-flop, which is synchro-
nously toggled by the oscillator output. The oscil-
lator output pulse also serves as a blanking pulse
to assure both output are never on simultane-
ously during the transition times. The width of the
blanking pulse is controlled by the value of C
T
.
The outputs may be applied in a push-pull con-
figuration in which their frequency is half that of
the base oscillator, or paralleled for single-ended
applications in which the frequency is equal to
that of the oscillator. The output of the error am-
plifier shares a common input to the comparator
with the current limiting at shutdown circuitry and
can be overridden by signals from either of these
inputs. This common point is also available exter-
nally and may be employed to control the gain of,
or to compensate, the error amplifier, or to pro-
vide additional control to the regulator.
RECOMMENDED OPERATING CONDITIONS
Supply voltage V
IN
Reference Output Current
Current trough C
T
Terminal
Timing Resistor, R
T
Timing Capacitor, C
T
8 to 40V
0 to 20mA
- 0.03 to -2mA
1.8 to 100KΩ
0.001 to 0.1µF
cording to the approximate formula:
f
=
1.18
R
T
C
T
where:
R
T
is in KΩ
C
T
is in
µF
f is in KHz
Pratical values of C
T
fall between 0.001 and
0.1µF. Pratical values of R
T
fall between 1.8 and
100KΩ. This results in a frequency range typically
from 120Hz to to 500KHz.
BLANKING
The output pulse of oscillator is used as a blank-
ing pulse at the output. This pulse width is con-
trolled by the value of C
T
.If small values of C
T
are
required for frequency control, the oscillator out-
put pulse width may still be increased by applying
a shunt capacitance of up to 100pF from pin 3 to
ground. If still greater dead-time is required, it
should be accomplished by limiting the maximum
duty cycle by clamping the output of the error am-
plifier. This can easily be done with the circuit be-
low:
Figure 6.
TYPICAL APPLICATIONS DATA
OSCILLATOR
The oscillator controls the frequency of the
SG3524 and is programmed by R
T
and C
T
ac-
SYNCRONOUS OPERATION
When an external clock is desired, a clock pulse
of approximately 3V can be applied directly to the
oscillator output terminal. The impedance to
ground at this point is approximately 2KΩ. In this
configuration R
T
C
T
must be selected for a clock
period slightly greater than that the external clock.
If two more SG2524 regulators are to be operated
synchronously, all oscillator output terminals
should be tied together, all C
T
terminals con-
nected to a single timing capacitor, and timing re-
sistor connected to a single R
T
terminal. The
other R
T
terminals can be left open or shorted to
V
REF
. Minimum lead lengths should be used be-
tween the C
T
terminals.
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