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March 1996
NDS351N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications in notebook
computers, portable phones, PCMCIA cards, and other
battery powered circuits where fast switching, and low
in-line power loss are needed in a very small outline
surface mount package.
Features
1.1A, 30V. R
DS(ON)
= 0.25
Ω
@ V
GS
= 4.5V.
Proprietary package design using copper lead frame for
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
I
SM
V
SD
Notes:
1. R
θ
JA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
θ
JC
is guaranteed by
design while R
θ
CA
is determined by the user's board design.
Maximum Continuous Drain-Source Diode Forward Current
Maximum Pulsed Drain-Source Diode Forward Current
Drain-Source Diode Forward Voltage
V
GS
= 0 V, I
S
= 1.1 A
(Note 2)
0.8
0.6
5
1.2
A
A
V
P
D
(
t
) =
R
θ
J A
t
)
(
T
J
−
T
A
=
T
J
−
T
A
R
θ
J C
R
θ
CA
t
)
+
(
=
I
2
(
t
) ×
R
DS
(
ON
)
D
T
J
Typical R
θ
JA
using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
模拟电子
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