Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
Dot Character VFD Controller/Driver IC
PT6314
DESCRIPTION
PT6314 is a VFD Controller/Driver IC utilizing CMOS technology providing 80 segment outputs and 24
grid outputs. It supports dot matrix displays of up to 16 columns x 2 lines, 20 columns x 2 lines or 24
columns x 2 lines. PT6314 also features a character generator ROM which stores 240 x 5 x 8 dos
characters. Pin assignments and application circuits are optimized for easy PCB layout and cost
saving advantages.
FEATURES
•
•
•
•
•
•
•
•
CMOS technology
Provides up to 80 x 8 display RAM
Capable of driving segment for cursor displays (48 units)
Built-in oscillation circuit
Parallel data input/output (switchable 4 or 8 bits) or serial data input/output
Alphanumeric and symbolic display via the built-in ROM (5 x 8 dots): 240 characters
Eight user-defined 5 x 8 dot character CGRAM
Display contents capability:
- 16 columns x 2(1) rows + 32(16) cursors
- 20 columns x 2(1) rows + 40(20) cursors
- 24 columns x 2(1) rows + 48(24) cursors
•
Custom ROM available (please contact PTC)
APPLICATIONS
•
Electronic equipment with VFD display
•
Microprocessor peripherals
PT6314 V1.3
-1-
March, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
Dot Character VFD Controller/Driver IC
PT6314
BLOCK DIAGRAM
OSC1 OSC2
CLK
VDD1 VDD2
VSS1
VSS2
SDO SLK /CLR LATCH
TESTOUT
TEST
IFSEL
/CS
RS/STB
R/W(/WR)
E(/RD)/SCK
SI/SO
DB0
DB1
DB2
DB3
DB4
DB5
DB7
/RESET
MPU
DS0
DS1
DLS
RL1
Oscillation
Circuit
Address
Counter
7
7
Timing
Generator
7
Display Data
RAM (DDRAM)
80x8 Bits
8
24
24 Bits
Shift Register
24
GR1
GR2
GR3
GR4
GR5
GR6
GR7
GR8
GR9
GR10
GR11
GR12
8
Instruction
Register
8
Instruction
Decoder
7
I/O
Buffer
8
Data
Register
8
8
7
8
Cursor Blink
Control Circuit
Grid Signal
Driver
Reset Circuit
Character
Generator
RAM (CGRAM)
8x5x8 Bits
5
Character
Generator
ROM (CGROM)
248x5x8 Bits
5
Parallel to Serial
Data Converter
80 Bits
Latch
80
Segment Signal Driver
80
80 Bits
Shift Register
GR22
GR23
GR24
SG1 SG2 SG3 SG4 SG5 SG6 SG7 SG8
SG79
SG80
PT6314 V1.3
-2-
March, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
Dot Character VFD Controller/Driver IC
PT6314
PIN CONFIGURATION
NC
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
NC
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD2
VSS2
VDD1
CLK
OSC2
OSC1
RESET
TEST
DLS
DS1
DS0
R/W
RS/STB
E/SCK
S1/S0
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
IFSEL
MPU
/CS
RL1
RL2
CLR
LATCH
SDO
SLK
TESTOUT
VSS1
VSS2
VDD2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NC
PT6314
NC
Note:
Pin No. 38 to 71, 73 to 108, 110 to 119 are used as Segment Signal Output Pins, Pin No.120 to 143 are
used as Grid Signal Output Pins and are configured according to the Tables shown in the Duty Ratio
Setting Section (see pages 7 to 13).
PT6314 V1.3
-3-
March, 2006
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
Dot Character VFD Controller/Driver IC
PT6314
PIN DESCRIPTION
Pin Name
VDD2
VSS2
VDD1
OSCO
OSC2
OSC1
/RESET
TEST
I/O
-
-
-
O
O
I
I
I
Description
Pin No.
VFD Driving Power Supply Pin
1, 36
VFD Driving Power Supply Pin
2, 35
Logic Power Supply Pin
3
Oscillation Signal Output Pin
4
Oscillation Output Pin
5
Oscillation Input Pin
6
Reset Pin
When this pin is set to “0”, all internal registers and commands are
7
initialized. The Segment and Grid Outputs are fixed to VDD.
Test Pin
0 or floating : the Normal Operation Mode
8
1:the Test Mode is active
Display Line Select Pin
This pin is used to select the number of display lines when
the
9
Power is ON, Reset or Resetting.
0: 1 line is selected (N=”0”)*
1: 2 lines are selected (N=”1”)*
Duty Select Pin
These pins set the duty ratio. The duty ratio is determined by the
10, 11
number of Grid.
Read/Write (Write) Signal Pin
Under the M68 Parallel Data Transfer Mode (R/W), this pin functions as
the Data Transfer Select Pin.
0: Write Function 1: Read Function
12
Under the i80 parallel data Transfer Mode (/WR), this pin is Write
Enable Pin. It writes data at the rising edge of this signal.
Under the Serial Transfer Mode, the Read or Write function is selected
by instruction and this pin is connect to either “H” or “L”.
Register Select/Strobe Pin
Under the Parallel Transfer Mode is selected, this pin acts as the
Register Select Pin.
13
0:Instruction Register (IR) 1: Data register (DR)
Under Serial Data Transfer Mode, this pin acts as the Strobe Input Pin.
Enable (Read)/Shift Clock
Under the M68 Parallel Data Transfer Mode (E), this pin functions as
the Write Enable Pin. Data is written at the falling edge.
Under the i80 Parallel Data Transfer Mode (/RD), this pin functions as
14
the Read Enable Pin. When this pin is set to “LOW”, data is outputted to
the Data Bus.
Under the Serial Data Transfer Mode, this pin functions as the Shift
Clock Input Pin. Data is written at the rising edge.
DLS
I
DS1, DS0
I
R/W(/WR)
I
RS/STB
I
E(/RD)/SCK
I
Note: *=N is the Display Line Select Flag in “Function Set” Command
PT6314 V1.3
-4-
March, 2006
Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
Dot Character VFD Controller/Driver IC
Pin Name
SI/SO
I/O
I/O
Description
PT6314
Pin No.
DB0 to DB7
I/O
IFSEL
MCU
/CS
RL1,RL2
I
I
I
I
/CLR
LATCH
SDO
SLK O
TESTOUT
VSS1
GR1 to GR24
SG1 to SG80
O
O
O
O
-
O
O
Serial Input/Output Pin
Under the Serial Data Transfer Mode, this pin functions as an I/O
Pin.
15
Under the Parallel Data Transfer Mode, this pin may be connected
to either “H” or “L”
Parallel Data Input/Output Pins
Under the Parallel Data Transfer Mode, these pins are used as I/O
16-23
Pin.
Under the 4-bit Transfer Mode, DB4 to DB7 are used.
I/F Select Pin
This pin is used to select the I/F mode: Serial or Parallel Transfer
24
0: Serial Data Transfer
1: Parallel Data Transfer
Interface Select Pin
This pin is used to select the interface mode: i80 or M68.
25
0: i80 CPU Mode
1: M68 CPU Mode
Chip Select Pin
26
When this pin is set to “L” the PT6314 is active.
Segment Output Select Pin
27, 28
This pins are used to set SG1 to SG80.
Extension Grid Driver Clear Signal Output Pin
Active: Low
The Grid Data stored in extension driver latch are outputted
29
when this pin is set to “HIGH”. If this pin is set to ”LOW”, the
extension driver outputs LOW.
Extension Grid Driver Latch Enable Signal Output Pin
30
Extension Grid Driver Serial Data Output Pin
31
Extension Grid Driver Shift Clock Output Pin
32
Rising Edge: Active
Test Pin for IC Testing only.
33
This pin should be “open”.
Logic Ground Pin
34
Grid Signal Output Pins
143-120
Segment Signal Output Pins
see (1)
Note: Refer to Duty Ratio Setting Section
PT6314 V1.3
-5-
March, 2006
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