1 MEG x 16
FPM DRAM
FPM DRAM
FEATURES
• JEDEC- and industry-standard x16 timing,
functions, pinouts, and packages
• High-performance, low-power CMOS silicon-gate
process
• Single power supply (+3.3V ±0.3V or 5V ±0.5V)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
• Optional self refresh (S) for low-power data
retention
• BYTE WRITE and BYTE READ access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
• FAST-PAGE-MODE (FPM) access
MT4C1M16C3, MT4LC1M16C3
For the latest data sheet revisions, please refer to the Micron
Web site:
www.micron.com/datasheets
PIN ASSIGNMENT (Top View)
42-Pin SOJ
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
NC
44/50-Pin TSOP
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
NC
OPTIONS
•
Voltage
1
3.3V
5V
• Packages
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
• Timing
50ns access
60ns access
• Refresh Rates
Standard Refresh (16ms period)
Self Refresh (128ms period)
• Operating Temperature Range
Commercial (0
o
C to +70
o
C)
Extended (-20
o
C to +80
o
C)
Part Number Example:
MARKING
LC
C
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
V
CC
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
V
SS
DJ
TG
-5
-6
None
S
2
None
ET
3
NOTE:
The # symbol indicates signal is active LOW.
1 MEG x 16 FPM DRAM PART NUMBERS
PART NUMBER
MT4LC1M16C3DJ-6
MT4LC1M16C3DJ-6 S
MT4LC1M16C3TG-6
MT4LC1M16C3TG-6 S
MT4C1M16C3DJ-6
MT4C1M16C3TG-6
SUPPLY PACKAGE REFRESH
3.3V
SOJ
Standard
3.3V
SOJ
Self
3.3V
TSOP
Standard
3.3V
TSOP
Self
5V
SOJ
Standard
5V
TSOP
Standard
MT4LC1M16C3DJ-5
NOTE:
1. The third field distinguishes the low voltage offering:
LC designates V
CC
= 3.3V and C designates V
CC
= 5V.
2. Contact factory for availability.
3. Available only on MT4C1M16C3 (5V)
GENERAL DESCRIPTION
The 1 Meg x 16 DRAM is a randomly accessed, solid-
state memory containing 16,777,216 bits organized in
a x16 configuration. The 1 Meg x 16 DRAM has both
BYTE WRITE and WORD WRITE access cycles via two
CAS# pins (CASL# and CASH#). These function identi-
cally to a single CAS# on other DRAMs in that either
CASL# or CASH# will generate an internal CAS#.
The CAS# function and timing are determined by
the first CAS# (CASL# or CASH#) to transition LOW and
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
84ns
110ns
50ns
60ns
20ns
35ns
25ns
30ns
15ns
15ns
30ns
40ns
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
1 MEG x 16
FPM DRAM
GENERAL DESCRIPTION (continued)
the last CAS# to transition back HIGH. Use of only one
of the two results in a BYTE access cycle. CASL#
transitioning LOW selects an access cycle for the lower
byte (DQ0-DQ7), and CASH# transitioning LOW se-
lects an access cycle for the upper byte (DQ8-DQ15).
Each bit is uniquely addressed through the 20 ad-
dress bits during READ or WRITE cycles. These are
entered ten bits (A0-A9) at a time. RAS# is used to latch
the first ten bits and CAS# the latter ten bits. The CAS#
function is determined by the first CAS# (CASL# or
CASH#) to transition LOW and the last one to transition
back HIGH. The CAS# function also determines
whether the cycle will be a refresh cycle (RAS#-ONLY)
or an active cycle (READ, WRITE, or READ-WRITE) once
RAS# goes LOW.
The CASL# and CASH# inputs internally generate a
CAS# signal that functions identically to a single CAS#
input on other DRAMs. The key difference is that each
CAS# input (CASL# and CASH#) controls its corre-
sponding DQ tristate logic (in conjunction with OE#
and WE#). CASL# controls DQ0-DQ7 and CASH# con-
trols DQ8-DQ15. The two CAS# controls give the
1 Meg x 16 DRAM BYTE WRITE cycle capabilities.
A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE#
or CAS, whichever occurs last. Taking WE# LOW will
initiate a WRITE cycle, selecting DQ0-DQ15. If WE#
goes LOW prior to CAS# going LOW, the output pin(s)
remain open (High-Z) until the next CAS# cycle. If WE#
goes LOW after CAS# goes LOW and data reaches the
output pins, data-out (Q) is activated and retains the
selected cell data as long as CAS# and OE# remain LOW
(regardless of WE# or RAS#). This late WE# pulse re-
sults in a READ-WRITE cycle.
The 16 data inputs and 16 data outputs are routed
through 16 pins using common I/O. Pin direction is
controlled by OE# and WE#.
FUNCTIONAL BLOCK DIAGRAM
WE#
CASL#
CASH#
DQ0
16
NO. 2 CLOCK
GENERATOR
DATA-OUT
BUFFER
10
CAS#
DATA-IN BUFFER
DQ15
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
10
COLUMN-
ADDRESS
BUFFER
REFRESH
CONTROLLER
COLUMN
DECODER
16
1,024
OE#
16
SENSE AMPLIFIERS
I/O GATING
REFRESH
COUNTER
10
ROW
DECODER
1,024 x 16
ROW-
ADDRESS
BUFFERS (10)
10
1,024
1,024 x 1,024 x 16
MEMORY
ARRAY
RAS#
NO. 1 CLOCK
GENERATOR
V
DD
V
SS
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
1 MEG x 16
FPM DRAM
GENERAL DESCRIPTION (continued)
The MT4LC1M16C3 must be refreshed periodically
in order to retain stored data.
and executing anyRAS# cycle (READ, WRITE) or RAS#
REFRESH cycle (RAS# ONLY, CBR or HIDDEN) so that
all 1,024 combinations of RAS# addresses (A0-A9) are
executed at least every 16ms (128ms on the “S” ver-
sion), regardless of sequence. The CBR REFRESH cycle
will also invoke the refresh counter and controller for
row-address control.
FAST PAGE MODE ACCESS
FAST-PAGE-MODE operations allow faster data op-
erations (READ, WRITE or READ-MODIFY-WRITE)
within a row-address-defined (A0-A9) page boundary.
The FAST-PAGE-MODE cycle is always initiated with a
row address strobed in by RAS#, followed by a column
address strobed in by CAS#. Additional columns may
be accessed by providing valid column addresses,
strobing CAS# and holding RAS# LOW, thus executing
faster memory cycles. Returning RAS# HIGH termi-
nates the FAST-PAGE-MODE operation.
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standbylevel. The chip is also preconditioned for the
next cycle during the RAS# HIGH time. Memory cell
data is retained in its correct state by maintaining power
BYTE ACCESS CYCLE
The BYTE WRITEs and BYTE READs are determined
by the use of CASL# and CASH#. Enabling CASL# will
select a lower byte access (DQ0-DQ7), while enabling
CASH# will select an upper byte access (DQ0-DQ15).
Enabling both CASL# and CASH# selects a WORD
WRITE cycle.
The 1 Meg x 16 DRAM may be viewed as two 1 Meg x
8 DRAMs that have common input controls, with the
exception of the CAS# inputs. Figure 1 illustrates the
BYTE WRITE and WORD WRITE cycles. Figure 2 illus-
trates BYTE READ and WORD READ cycles.
WORD WRITE
LOWER BYTE WRITE
RAS#
CASL#
CASH#
WE#
LOWER BYTE
(DQ0-DQ7)
OF WORD
STORED
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
0
0
1
0
0
0
0
0
INPUT
DATA
STORED
DATA
0
0
1
0
0
0
0
0
STORED
DATA
0
0
1
0
0
0
0
0
INPUT
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
STORED
DATA
1
1
0
1
1
1
1
1
0
1
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
UPPER BYTE
(DQ8-DQ15)
OF WORD
0
1
0
0
0
0
1
0
1
0
1
1
1
1
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
ADDRESS 0
ADDRESS 1
X = NOT EFFECTIVE (DON'T CARE)
Figure 1
WORD and BYTE WRITE Example
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
1 MEG x 16
FPM DRAM
Additionally, both bytes must always be of the same
mode of operation if both bytes are active. A CAS#
precharge must be satisfied prior to changing modes of
operation between the upper and lower bytes. For ex-
ample, an EARLY WRITE on one byte and a LATE WRITE
on the other byte are not allowed during the same cycle.
However, an EARLY WRITE on one byte and a LATE
WRITE on the other byte, after a CAS# precharge has
been satisfied, are permissible.
the choice of a fully static, low-power data retention
mode or a dynamic refresh mode at the extended re-
fresh period of 128ms, or 125µs per row, when using a
distributed CBR REFRESH. This refresh rate can be
applied during normal operation, as well as during a
standby or battery backup mode.
The self refresh mode is terminated by driving
RAS# HIGH for a minimum time of
t
RPS. This delay
allows for the completion of any internal refresh cycles
that may be in process at the time of the RAS# LOW-
to-HIGH transition. If the DRAM controller uses a dis-
tributed CBR refresh sequence, a burst refresh is not
required upon exiting self refresh. However, if the
DRAM controller utilizes a RAS#-ONLY or burst CBR
refresh sequence, all 1,024 rows must be refreshed us-
ing a minimum
t
RC refresh rate prior to resuming nor-
mal operation.
DRAM REFRESH
Preserve correct memory cell data by maintaining
power and executing any RAS# cycle (READ, WRITE) or
RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN)
so that all 1,024 combinations of RAS# addresses are
executed within
t
REF (MAX), regardless of sequence.
The CBR and EXTENDED and SELF REFRESH cycles
will invoke the internal refresh counter for automatic
RAS# addressing.
An optional self refresh mode is available on the “S”
version. The self refresh feature is initiated by per-
forming a CBR REFRESH cycle and holding RAS# LOW
for the specified
t
RASS. The “S” option allows the user
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
WORD READ
RAS#
LOWER BYTE READ
CASL#
CASH#
WE#
LOWER BYTE
(DQ0-DQ7)
OF WORD
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
UPPER BYTE
(DQ8-DQ15)
OF WORD
ADDRESS 0
Z = High-Z
ADDRESS 1
Figure 2
WORD and BYTE READ Example
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
1 MEG x 16
FPM DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
Pin Relative to V
SS
3.3V ..................................................... -1V to +4.6V
5V ........................................................... -1V
TO
+7V
Voltage on NC, Inputs or I/O Pins Relative to V
SS
3.3V ..................................................... -1V to +5.5V
5V ........................................................... -1V
TO
+7V
Operating Temperature
T
A
(commercial) ...................................... 0°C to +70°C
T
A
(extended "ET") ............................ -20°C to +80°C
Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ........................................................ 1W
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 5, 6; notes can be found on page 9); V
CC
(MIN)
≤
V
CC
≤
V
CC
(MAX)
3.3V
PARAMETER/CONDITION
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE:
Valid Logic 1; All inputs, I/Os and any NC
INPUT LOW VOLTAGE:
Valid Logic 0; All inputs, I/Os and any NC
INPUT LEAKAGE CURRENT:
Any input at V
IN
(0V
≤
V
IN
≤
V
CC
+ 0.3V);
All other pins not under test = 0V
OUTPUT HIGH VOLTAGE:
I
OUT
= -2mA
OUTPUT LOW VOLTAGE:
I
OUT
= 2mA
OUTPUT LEAKAGE CURRENT:
Any output at V
OUT
[0V
≤
V
OUT
≤
V
CC
(MAX)];
DQ is disabled and in High-Z state
SYMBOL
V
CC
V
IH
V
IL
I
I
MIN
3
2
-1.0
-2
MAX
3.6
5.5
0.8
2
MIN
4.5
2.4
-0.5
-2
5V
MAX UNITS NOTES
5.5
V
CC
+ 1
0.8
2
V
V
V
µA
V
OH
V
OL
I
OZ
2.4
–
-5
–
0.4
5
2.4
–
-5
–
0.4
5
V
V
µA
1 Meg x 16 FPM DRAM
D51_5V_B.p65 – Rev. B; Pub 3/01
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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