an Intel company
10 Gbit/s
Transmitter MUX
with Re-timing
GD16585/GD16589
(FEC)
Preliminary
General Description
GD16585 and GD16589 are transmitter
chips used in SDH STM-64 and SONET
OC-192 optical communication systems.
The device is available in two versions:
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GD16585 for 9.5328 Gbit/s.
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GD16589 for 10.66 Gbit/s with
Forward Error Correction (FEC).
Except the different operating bit rate the
two versions are functional identical.
The transmitter integrates the main func-
tions of the serializer which are:
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Clock Multiply Unit (CMU)
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16:1 Multiplexer in a single monolithic
IC.
The CMU consists of Phase Locked
Loop (PLL) controlled from an external
reference clock. The PLL characteristics
are controlled by an external loop filter al-
lowing the user to optimize the jitter
perfomance of the device.
The 16:1 Multiplexer accepts 16 parallel
input bits at 622.88 Mbit/s (or 666 Mbit/s)
that are serialized into a 9.9538 Gbit/s (or
10.66 Gbit/s) data stream. The serialized
data stream is re-timed by the high-
speed clock from the VCO.
The parallel input interface features
GIGA’s unique self-synchronizing dy-
namic phase alignment scheme that al-
lows both:
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Source synchronous counter clocking
for OIF99.102.5 interfaces.
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Forward clocking with phase nulling
and jitter clean-up of the clock.
These schemes enable the serializer to
absorb output delay variations from the
upstream System ASIC without use of
initialization or reset.
The data and clock inputs to the MUX
are LVDS and the output data is CML
compatible.
The device operates from a dual -5.2 V
and +3.3 V power supply. The power dis-
sipation is 2.2 W, typical.
The device is manufactured in a Silicon
Bipolar process and packaged in an 132
balls 13 × 13 mm Ceramic/Plastic Ball
Grid Array (CBGA).
Features
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PLL based CMU with on-chip 10 GHz
or 10.66 GHz VCO.
16:1 Multiplexer with a last stage
re-timing.
OIF99.102.5 compliant timing .
LVDS compatible parallel data and
clock inputs
CML compatible serial data output.
155 MHz or 622 MHz reference clock
input (selectable).
Divide by 16 clock output.
PLL out of lock detector.
Dual supply operation: -5.2 V and
+3.3 V
Low power dissipation: 2.2 W (typ.).
Available in three package versions:
– EB: 132 ball (16 mill) Ceramic
BGA 13 × 13 mm
– EF: 132 ball (20 mill) Ceramic
BGA 13 × 13 mm
– FB: 132 ball (20 mill) Plastic
BGA 13 × 13 mm
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DI0
DIN0
Parallel
Input Data
DI15
DIN15
FF
VCUR
OUT
OUTN
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16:1
Multiplexer
VCO
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Available in two versions:
– GD16585 for 10 Gbit/s
– GD16589 for 10.66 Gbit/s
VCTL
SEL1
SEL2
CKOUT
CKOUTN
CKI
CKIN
Phase
Selector
Timing
Control
Phase
Frequency
Detector
Applications
PCTL
(PHIGH)
(PLOW)
NLDET
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PFCX
TCK
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Telecommunication systems:
– SDH STM-64
– SONET OC-192
– Optical Transport Networking
(OTN)
– FEC applications
Fibre optic test equipment.
PCTLX
SGNX
SEL3
REFCK/N VCC VDD VDDO VDDA VEE
Data Sheet Rev.: 13
Functional Details
The main function of GD16585/GD16589
is as transmitter in STM-64 /OC-192 and
OTN optical communication systems.
It integrates:
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Voltage Controlled Oscillator (VCO)
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Phase and Frequency Detector (PFD)
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16:1 Multiplexer
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Re-timing of output data.
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Phase nulling circuit for interfacing in-
put data and clock.
The timing relation is OIF99.102.5 com-
plaint with SEL1,2 = 1,1 (0 V).
The select inputs (SEL1-3 and SGNX)
are low-speed ECL compatible inputs,
which can be connected directly to the
negative supply rails (0 / -5.2 V).
The PCB layout of the loop filter and the
connecting lines between PCTL and
VCTL are critical for the jitter perfor-
mance of the device. The external com-
ponents and the artwork should be
placed very close to the pins at
GD16585.
If the PHIGH and PLOW outputs are not
used they must be shorted to VDD (0 V),
please refer to
Figure 1.
Bit Order
The parallel data input is multiplexed with
DI0 as the first sent bit, DI1 as the sec-
ond sent bit and with DI15 as the last
sent bit in a 16 bit frame.
Note:
This bit naming covention is
opposite to OIF99.102.5
For OIF interfaces the data pins should
be connected as shown in the following
table.
Input Pin:
DI0/DIN0
DI1/DIN1
DI2/DIN2
DI3/DIN3
DI4/DIN4
DI5/DIN5
DI6/DIN6
DI7/DIN7
DI8/DIN8
DI9/DIN9
DI10/DIN10
DI11/DIN11
DI12/DIN12
DI13/DIN13
DI14/DIN14
DI15/DIN15
CKI
CKIN
OIF:
TXDATA15_P/N
(MSB)
TXDATA14_P/N
TXDATA13_P/N
TXDATA12_P/N
TXDATA11_P/N
TXDATA10_P/N
TXDATA9_P/N
TXDATA8_P/N
TXDATA7_P/N
TXDATA6_P/N
TXDATA5_P/N
TXDATA4_P/N
TXDATA3_P/N
TXDATA2_P/N
TXDATA1_P/N
TXDATA0_P/N
(LSB
TXCLK_P
TXCLK_N
VCO
The VCO is an LC-type differential oscil-
lator controlled by pin VCTL and with a
tuning range of
±5
%. The VCO and the
clock divider circuit generate the clock
signals and load pulses needed for
multiplexing and timing control.
With the VCTL voltage at -3 V the VCO
frequency is fixed at 9.953 GHz (for
GD16585) and by changing the voltage
from 0 to –5.2 V the frequency is con-
trolled from 9 GHz to 10.2 GHz. The
modulation bandwidth of VCTL is
90 MHz.
The Outputs
The output of the MUX stage is retimed
by the 10 GHz (or 10.66 GHz) clock and
the output driver is a Current Mode Logic
(CML) output with internal 50
W
termina-
tion resistors.
The serial output driver is internally termi-
nated with 50
W
resistors to 0 V. The out-
put should be terminated externally with
50
W
at the receive end and should be
used differential. Both OUT and OUTN
are best terminated with the same load
resistor e.g. 50
W,
an asymmetric loading
will decrease the performance of the out-
put due to reflections.
Both outputs
OUT/OUTN are not ESD
protected
and extra precautions should
be taken when handling the outputs (the
internal 50
W
resistor provides some
ESD hardness making the ouput low
impedance).
A divide by 16 clock output from the
CMU is available at CKOUT/N for jitter
measurement and test purpose. These
outputs are differential open collector
with a 8 mA output current. They are ter-
minated externally with resistors and can
be terminated to the positive 3.3 V
supply. The clock outputs should be ter-
minated even though they are not used.
PLL out of lock detect signal (NLDET) is
provided as a status signal of the PLL. It
compares the VCO clock with the refer-
ence clock and is low whenever the VCO
is locked to the reference clock. The
NLDET is an open collector output and
must be terminated by an external resis-
tor.
The Reference Clock
The PFD is made with digital set/reset
cells giving it a true phase and frequency
characteristic. The reference clock
(REFCK/REFCKN) to the PFD is 155 or
622 MHz selectable by SEL3.
The reference clock input is a CML input
with 50
W
internal termination resistors.
The reference clock should be used dif-
ferential for obtaining lowest clock jitter.
The PLL synchronizes the VCO to the
external reference clock. Spectral noise
from the reference clock, within the PLL
bandwidth, will be multiplied and added
to the serial output by the divider ratio
between the VCO and reference clock
i.e. N = 16 or in terms of phase noise as
20Log(16) = 24 dB (or 36 dB at N = 64).
A low noise reference clock with low
clock jitter is required in order to fulfill the
ITU-T jitter requirements.
Loop Filter for the CMU
Inputs
The parallel data (DIx/DINx) and clock
(CKI/CKIN) inputs are LVDS compatible
with internal differential 100
W
resistors.
The set-up and hold time between input
clock and data is selectable in four set-
tings by SEL1-2.
An external passive loop filter is used,
consisting of a resistor and a capacitor
driven from the PCTL pin, which outputs
the phase and frequency information
from the PFD. The values of the external
components determines the
characterisitcs of the PLL e.g. bandwidth
and transfer function. For recommended
loop filter values see
Figure 1.
The Output Voltage Control
The serial output voltage swing at
OUT/OUTN is controlled by VCUR in the
range from 0.1 V to 0.8 V. The voltage
swing is increased by increasing the
VCUR voltage and the output is off at
voltages below VEE +2 V.
Data Sheet Rev.: 13
GD16585/GD16589
Page 2 of 17
If no adjustement is needed the VCUR
can be lefted open.
With AC coupled outputs the VCUR pin
must not be directly connected to 0 V
which may cause the output stage to
saturate deteriorating the eye-diagram.
Refer to
Figure 1
for the recommended
set-up of VCUR.
Thermal Condition
The component dissipates 2.2 W with a
–5.2 V and +3.3 V voltage supply.
The die is mounted in a cavity on a metal
pad directly connected to the center balls
(E4-9, F4-9, G4-9, and H4-9).
It is important to have a good thermal
connection from the center balls of the
package to the ambient environment to
ensure the best thermal conditions.
Note:
To obtain T
CASE
< 70°C,
the PGBA (compared to the
CBGA) requires additional
cooling on the case,
For details, please refer to
Application Note “ PBGA -
Thermal data....”.
Timing to the System ASIC
The component supports source
synchronouse clocking for OIF99.102.5
interface (311 MHz clock mode is not
supported) and forward clocking with
phase nulling and jitter clean-up of the
reference clock. With a OIF interface a
phase adjusted source clock is feed back
to the System ASIC and data and clock
are feed forward to the high-speed MUX.
The phase difference between the for-
ward clock (CKI/CKIN) and the internal
load pulse is detected by the Phase and
Frequency Detector (PFCX) and the
Phase Information (PCTLX) are use to
control the phase and frequency of the
external VCXO (622 MHz). The phase
adjusted output clock of the VCXO can
be used either as a source (counter)
clock to the System ASIC (OIF99.102.5
in 622 MHz clock mode) or as a jitter
clean reference clock (REFCK/N) to the
on-chip CMU.
The phase information at PCTLX is fil-
tered in an external low pass filter con-
sisting of a capacitor and a resistor. For
recommended component values, please
refer to
Figure 1.
10.66 Gbit/s Application
A version of the transmitter with a bit rate
of 10.66 Gbit/s for Optical Transport Net-
working (OTN) and Forward Error Cor-
rection (FEC) application is available.
The part number is GD16589.
The functionality and the pin-out are
identically to the GD16585.
The center frequency of the VCO
(10.66 GHz) is the only difference to the
GD16585.
Package
GD16585 and GD16589 are packaged in
an 132 ball Ceramic/Plastic BGA
(13×13 mm). For the package outline,
please refer to
Figure 14 and 15.
In ceramic packages following pin pairs
are individually shorted inside the pack-
age and mainly used as power pins:
C3/D3, C4/D4, C5/D5, C8/D8, C9/D9,
C10/D10, J3/K3, J4/K4, J5/K5, J8/K8,
J9/K9, and J10/K10, please refer to
“Package Pinout”
Figure 8
on
page 8.
Data Sheet Rev.: 13
GD16585/GD16589
Page 3 of 17
Application
0V
Framer
16
+3.3V
VCC
VDD/VDDA
(VDDO)
16
DI0..15
DIN0..15
CKI
CKIN
OUT
OUTN
10Gbit/s
Output
VCO
0V
PCTLX
1kW
-5.2V
10nF
GD16585/GD16589
REFCK
REFCKN
500W
-5.2V
VCC
100nF
330W
VCUR
10kW
4.7kW
50W
CKOUT
NLDET
CKOUTN
VDD
Out of
Lock
+
-
VCC
0V
SEL1
SEL2
SEL3
PHIGH
PLOW
VCTL
SGNX
PCTL
0V
622MHz
155MHz
0V
-5.2V
0V
-5.2V
2.2kW 33nF
VDDA
VEE
-5.2V
Figure 1.
Application Information, OIF interface to the Framer.
VDD
VEE
VDDO
VEE
Pin D1
C
Pin D2
C
C
C
For all VDD pins refer to Pin List
C
C
C
C
C
C
Pin J8
C
Pin K8
C
10
m
F
Pin C2
C
C
A7
C
K5
VDDA
10
m
F
VCC
VDD
Pin D11
C
C
Pin M3
C
10
m
F
C is 10nF parallel with 100pF.
VEE, VCC, VDDA pins refer to Pin List
Figure 2.
De-coupling of the Power Supply
Data Sheet Rev.: 13
GD16585/GD16589
Page 4 of 17
10 Gbit/s Output Interface
GD16585/GD16589
0V
Driver
50W
50
W
MSL
OUTN
50W
OUT
VCUR
-5.2V
Figure 3.
10 Gbit/s outputs (OUT/OUTN), DC coupled.
GD16585/GD16589
0V
Driver
50W
100nF
OUTN
50
W
MSL
50W
OUT
VCUR
-5.2V
Figure 4.
Note:
10 Gbit/s outputs (OUT/OUTN), AC coupled.
With AC coupled outputs VCUR
must not
be connected directly to 0 V.
Data Sheet Rev.: 13
GD16585/GD16589
Page 5 of 17
FPGA/CPLD
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