Enhanced Mini-ACE -
A New Generation of
MIL-STD-1553 Terminals
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
RT-only and BC/RT/MT versions.
One inch square package, pin-compatible
with Mini-ACE (Plus)
Option for 64K-word internal RAM,
with RAM parity.
Choice of 5V or 3.3V internal logic.
5V-only transceivers, with a choice of
trapezoidal or McAir compatible
transmitters.
BC architecture providing functionality
for highly autonomous message
sequence control.
BC general purpose queue.
RT global circular buffer.
RT interrupt status queue.
RT Auto-boot option
Additional interrupt conditions and
filtering capability.
Reduced maximum holdoff time for
shared RAM host interface.
Increased request-to-grant time for DMA
host interface.
Supports 10, 12, 16, or 20 MHz clock
inputs.
Comprehensive, autonomous built-in
self-test.
In its continuing role as the leading supplier of components
and other products to the MIL-STD-1553 community, DDC is
pleased to announce the introduction of the Enhanced
Mini-ACE series of MIL-STD-1553 terminals. The Enhanced
Mini-ACE series represents DDC's fifth generation of
complete data bus terminals for DDC, following the AIM-HY,
AIM-HY'er, ACE, and Mini-ACE (Plus) series.
Beyond providing backfit compatibility with the Mini-ACE and
Mini-ACE Plus series terminals, the Enhanced Mini-ACE
series offers additional functionality in many areas. These
include:
Backwards Compatibility
Like the ACE and Mini-ACE, the Enhanced Mini-ACE is
available in both BC/RT/MT and RT-only configurations. The
Enhanced Mini-ACE is available in the identical 1.0 by 1.0
inch co-fired ceramic package as the Mini-ACE and Mini-ACE
Plus. The choice of packages includes 72-pin flatpack or
formed gull lead. In addition to providing a myriad of new
features, the Enhanced Mini-ACE provides pin compatibility
and software back compatibility to the ACE, Mini-ACE and
Mini-ACE Plus. This allows re-usability of software code
written for earlier generation products.
Flexibility in voltages and clock
frequencies
The Enhanced Mini-ACE 1553 terminals are available in
options in which the internal logic circuitry may be powered by
either 5V or 3.3V. Use of the 3.3V option reduces power
consumption and provides increased flexibility in system
interfacing. Additional flexibility is provided as the Enhanced
Mini-ACE terminals may be operated with a choice of four
clock input frequencies: 16 MHz, 12 MHz, 10 MHz, or 20
MHz.
New transceivers
The transceivers in the Enhanced Mini-ACE MCMs are
completely monolithic, needing only a +5 volt power supply,
and requiring no additional external components except for
decoupling capacitors. The Enhanced Mini-ACE terminals
consume and dissipate very low power, with a
typical dissipation under 0.5 watts at idle, and less than 1.7
watts at 100% duty cycle. The Enhanced Mini-ACE is
available with transceivers which transmit trapezoidal wave-
forms for MIL-STD-1553A/B compliance, as well as versions
that transmit waveforms providing compatibility to McAir
specs. In addition to eliminating the need for power supplies
for other voltage(s), the use of a 5V transceiver entails the
use of a step-up, rather than step-down isolation
transformer. This increases the terminal's inherent input
impedance, reducing the demands on transformers and
system layout in meeting the MIL-STD-1553 impedance
requirement.
Improved Host Interface
Like the ACE and Mini-ACE series, the Enhanced Mini-ACE
supports a wide variety of processor interface configura-
tions. These include shared RAM and DMA configurations,
straightforward interfacing for 16-bit and 8-bit buses,
support for both non-multiplexed and multiplexed
address/data buses, non-zero wait mode for interfacing to
processor address/data buses, and zero wait mode for
interfacing (for example) to microcontroller I/O ports. In
addition, the Enhanced Mini-ACE provides two major
improvements: (1) reduced maximum host access time for
shared RAM mode; and (2) increased DMA grant time for
the transparent/DMA mode.
Reduced maximum host access time
For the previous generation ACE and Mini-ACE terminals,
the maximum host holdoff time (time prior to the assertion
of the READYD* handshake signal) is 10 internal word transfer
cycles, resulting in an overall maximum holdoff time of
approximately 2.8
µs,
using a 16 MHz clock. With the Enhanced
Mini-ACE, this worst-case holdoff time is reduced significantly, to
a single internal transfer cycle. This results in a maximum
overall host transfer cycle time of approximately 500 ns at 16
MHz.
Increased DMA grant time
For the ACE and Mini-ACE in DMA mode, the maximum
request-to-grant time, which occurs prior to an RT start-of-
message sequence, is 4.0
µs
with a 16 MHz clock, or
3.5
µs
with a 12 MHz clock. For the Enhanced Mini-ACE
functioning as a MIL-STD-1553B RT, this time increases to
8.5
µs
at 10 MHz, 10
µs
at 16 MHz, 9
µs
at 12 MHz, and
10.5
µs
at 20 MHz. This provides greater flexibility, particu-
larly for systems in which a host has to arbitrate among
multiple DMA requestors.
+5V-RAM/UPADDREN
TX/RX_A
4K X 16
OR
64K X 17
SHARED
RAM
TRANSCEIVER
A
DATA
BUFFERS
PROCESSOR
DATA BUS
CH. A
TX/RX_A
TRANSMITTER
INHIBITS
TX_INH_A
TX_INH_B
TX/RX_B
DATA BUS
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
D15-D0
ADDRESS BUS
ADDRESS
BUFFERS
A15/CLK_SEL_1,
A14/CLK_SEL_0,
A13/Vcc,
A12/RTBOOT,
A11-A0
PROCESSOR
ADDRESS BUS
CH. B
TRANSCEIVER
B
TX/RX_B
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
RT ADDRESS
AND
ADDRESS LATCH
RTAD4-RTAD0, RTADP
RT-AD-LAT
INCMD/MCRST
MISCELLANEOUS
CLK_IN,
MSTCLR,SSFLAG/EXT_TRG
Figure 1. Block diagram
New Architectural Features: Bus Controller Mode
Multiprotocol Compliance
Like the ACE and Mini-ACE, the Enhanced Mini-ACE
provides full compliance to all of the commonly used data
bus standards, including MIL-STD-1553A, MIL-STD-1553B
Notice 2, STANAG 3838, General Dynamics 16PP303, and
McAirA3818, A5232, and A5690. For BC mode, the
appropriate protocol for individual RTs may be programmed
on a message-by-message basis.
Message sequence control
One of the major new architectural features of the Enhanced
Mini-ACE series is its advanced capability for BC message
sequence control. The Enhanced Mini-ACE supports highly
autonomous BC operation, which greatly offloads the band-
width of the host processor.
2
The operation of the Enhanced Mini-ACE message
sequence control is illustrated in Figure 2. The BC message
sequence control involves an instruction list pointer register;
an instruction list, which contains multiple 2-word entries;
a message control/status stack, which contains multiple
8-word or 10-word descriptors; and data blocks for
individual messages.
BC INSTRUCTION
LIST
Table 1. BC Instructions for Message Sequence Control
Instructions
(acronym, op-code)
Execute Message (XEQ - 01h)
Jump (JMP - 02h)
Subroutine Call (CAL - 03h)
Subroutine Return (RTN - 04h)
Generate Interrupt (IRQ - 06h)
Halt (HLT - 07h)
Parameter
Message control/status block address
Instruction list jump address
Instruction list call address
---
Interrupt bit pattern
---
Delay time
---
Time value
Time value
Set/clear bits
Time Value
Time Value
---
---
---
Immediate value
Memory address
---
Message control/status block address
---
BC INSTRUCTION
LIST POINTER REGISTER
INITIALITIZE BY REGISTER
0D (RD/WR); READ CURRENT
VALUE VIA REGISTER 03
(RD ONLY)
MESSAGE
CONTROL/STATUS
BLOCK
OP CODE
PARAMETER
(POINTER)
BC CONTROL
WORD
COMMAND WORD
(Rx Command for
RT-to-RT transfer)
DATA BLOCK POINTER
DATA BLOCK
TIME-TO-NEXT MESSAGE
TIME TAG WORD
BLOCK STATUS WORD
Delay (DLY - 08h)
Wait until frame time = 0 (WTF - 09h)
Compare to Frame Time Counter
(CFT - 0Ah)
Compare to Message Time Counter
(CMT - 0Bh)
Set/Clear/Toggle General Purpose Flag
Bits (FLG - 0Ch)
Time Tag Counter <--- Time Value
(LTT – 0Dh)
Frame Time Register <--- Time Value
(LFT - 0Eh)
Start Frame Time Counter
(SFT - 0Fh)
GP Queue <--- Time Tag Register
(PTT – 10h)
GP Queue <--- Block Status Word
(PBS – 11h)
GP Queue <--- Immediate
(PSI - 12h)
GP Queue <--- Data (memory address)
(PSM - 13h)
Wait until external trigger 0 --->1
(WTG – 14h)
Execute and Flip
(XQF - 15h)
Trap (TRP - 00h, 16h-1Fh)
LOOPBACK WORD
RT STATUS WORD
2nd (Tx) COMMAND WORD
(for RT-to-RT transfer)
2nd RT STATUS WORD
(for RT-to-RT transfer)
Figure 2. BC Message Sequence Control
The instruction list pointer register is initialized by the host
processor, and is incremented by the BC message
sequence control processor. During operation, the message
sequence control processor fetches the operation refer-
enced by the message sequence control program counter
register.
Op Codes
The instruction list pointer references a pair of words in the
instruction list: an op code word, followed by a parameter
word. The format of the op code word, which is illustrated in
Figure 3, includes a 5-bit op code field and a 5-bit condition
code field. The op code identifies the instruction to be
executed by the BC message sequence controller. Most of
the operations are conditional, with execution dependent on
the contents of the condition code field. The condition code
field identifies the particular condition and its logic sense
("1" or "0") on which the conditional execution is dependent.
Table 1 lists all the op codes, along with their acronym, code
value, and parameter. Table 2 defines the condition codes.
As shown in Table 1, many of the operations include a
single-word parameter. For an XEQ (execute message)
operation, the parameter is a pointer to the start of the
message's control/status block. For other operations, the
15
1
14
13
12
11
10
9
8
0
parameter may be an address, a time value, an interrupt
pattern, a mechanism to set or clear general purpose flag
bits, or an immediate value. For several op codes, the para-
meter is "don't care" (not used).
As described above, some of the op codes will cause the
message sequence control processor to execute messages.
In this case, the parameter references the first word of a
message control/status block. With the exception of
RT-to-RT transfer messages, all message status/control
blocks are eight words long: a block control word, time-to-
next-message parameter, data block pointer, command
word, status word, loopback word, block status word, and
time tag word.
7
1
6
0
5
1
4
0
3
2
1
0
OpCode Field
Condition Code Field
Figure 3. BC Op Code Format
3
Table 2. Condition Codes
BIT
CODE
0000
0001
0002
NAME
INVERSE
(Bit 4 = 0) (Bit 4 = 1)
LT/GP0
EQ/GP1
GP2
GT/GP0*
NE/GTGP*
GP2*
FUNCTIONAL DESCRIPTION
Less Than Flag set or cleared after CFT or CMT operation / Also BIT Flag indicates BIT
passed or failed. Also, General Purpose Flag 0 set or cleared by FLG operation.
Equal Flag set or cleared after CFT or CMT operation / Also BIT Flag indicates BIT passed or failed. Also, General
Purpose Flag 1 set or cleared by FLG operation.
General Purpose Flags set or cleared by FLG operation or by host processor. The host processor will set and
clear these flags in the same way as the FLG instruction; i.e., the host may set, clear, toggle, and not change the
status of each of the eight flags using the sixteen bits.
0003
0004
0005
0006
0007
0008
0009
GP3
GP4
GP5
GP6
GP7
NORESP
FMT ERR
GP3*
GP4*
GP5*
GP6*
GP7*
RESP
FMT ERR*
Indicates that an RT has either not responded or has responded later than the BC No Response Timeout time.
FMT ERR indicates that the RT response to the most recent message contained one or more violations of the
1553 message validation criteria, or the status word received from a responding RT contained an incorrect RT
address field.
For the most recent message, GD BLK XFER will be set to logic "1" following completion of a valid (error-free)
RT-to-BC transfer, RT-to-RT transfer, or transmit mode code with data message. BAD BLK XFER is set to logic
"1" following an invalid message.
MASKED STATUS SET indicates that one (or more) of the Status Mask bits in the BC Control Word is logic "0"
and
the corresponding bit(s) is (are) set to logic "1" in the received RT Status Word.
BAD MESSAGE indicates either a format error, loop test fail, or no response error for the most recent message.
These two bits reflect the retry status of the most recent message. The number of times that the message was
retried is delineated by these two bits as shown below:
Number of
Message Retries
RETRY COUNT 1 RETRY COUNT 0
0
0
0
0
1
1
1
0
N/A
1
1
2
Always a logic 1 for unconditional operations. The inverse (NEVER) can be used to implement a NOP instruction.
000A
GD BLK
XFER
MASKED
STATUS
SET
BAD
MESSAGE
RETRY0
RETRY1
BAD BLK
XFER
MASKED
STATUS
CLR
GOOD
MESSAGE
RETRY0*
RETRY1*
000B
000C
000D
000E
000F
ALWAYS
NEVER
In the case of an RT-to-RT transfer message, the size of the
message control/status block increases to 16 words.
However, in this case, the last six words are not used; the
ninth and tenth words are for the second command word
and second status word.
The third word in the message control/status block is a
pointer that references the first word of the message's Data
Word block. Note that the Data Word block stores only Data
Words, which are to be either transmitted or received by the
BC. By segregating Data Words from Command Words,
Status Words, and other control and "housekeeping"
functions, this architecture facilitates the formation of
convenient, usable data structures, such as circular buffers
and double buffers.
Other operations support program flow control; i.e., jump
and call capability. The call capability includes maintenance
of a call stack; there is also a return instruction. Other op
codes may be used to invoke BIT (built-in test); delay for a
specified time; start a new BC frame; wait for an external
trigger to start a new frame; do comparisons based on
frame time and time-to-next message; load the time tag or
frame time registers; halt; and issue host interrupts. In the
case of host interrupts, the message control processor
passes a 4-bit user-defined interrupt vector to the host, by
means of the Enhanced Mini-ACE's Interrupt Status Register.
The purpose of the FLG instruction is to enable the
message sequence controller to set, clear, toggle, or "don't
change" the value(s) of any or all of the eight general
purpose condition flags.
The Enhanced Mini-ACE BC message sequence control
capability allows a high degree of offloading of the host
processor. This includes utilizing the various timing func-
tions to enable autonomous structuring of major and minor
frames. In addition, by implementing conditional jumps and
subroutine calls, the message sequence control processor
greatly simplifies the insertion of asynchronous, or "out-of-
band" messages.
Execute and Flip Operation
The Enhanced Mini-ACE BC's XQF, or "Execute and Flip"
operation, provides some unique capabilities. Following
execution of this unconditional instruction’s message, if the
condition code tests TRUE, the BC will modify the value of
the current XQF instruction's pointer parameter by toggling
bit 4 in the pointer. That is, if the condition flag tests true, the
value of the parameter will be updated to the value (old
address XOR 0010h). As a result, the next time that this line
in the instruction list is executed, the Message
Control/Status Block at the updated address (old address
XOR 0010h), rather than the one at the old address, will be
processed. The operation of the XQF instruction is
illustrated in Figure 4.
4
(part of) BC INSTRUCTION LIST
XQF
POINTER
MESSAGE
CONTROL/STATUS
BLOCK 0
XX00h
DATA BLOCK 0
There are multiple ways of using the "execute and flip"
functionality. One is to facilitate the implementation of a
double buffering data scheme for individual massages. This
allows the message sequence control processor to
"ping-pong" between a pair of data buffers for a particular
message. By so doing, the host processor can access one
of the two Data Word blocks, while the BC reads or writes
the alternate Data Word block.
A second application of the "execute and flip" capability is in
association with message retries. This allows the BC to
switch buses permanently for all future times that the same
message is to be processed. This not only provides a high
degree of autonomy from the host CPU, but saves BC
bandwidth by eliminating future attempts to process
messages on an RT's failed channel.
General Purpose Queue
The Enhanced Mini-ACE BC allows for the creation of a
general purpose queue. This data structure provides a
means for the message sequence processor to convey
information to the BC host. The BC op code repertoire
provides mechanisms to push various items on this queue.
These include the contents of the Time Tag Register, the
Block Status Word for the most recent message, an
immediate data value, or the contents of a specified
memory address.
MESSAGE
CONTROL/STATUS
BLOCK 1
XX00h
DATA BLOCK 1
Figure 4. Execute and Flip (XQF) Operation
New Architectural Features: RT Mode
Multiprotocol Compliance
Like the ACE and Mini-ACE, the Enhanced Mini-ACE
provides full compliance to all of the commonly invoked data
bus standards, including MIL-STD-1553A, MIL-STD-1553B
Notice 2, STANAG 3838, General Dynamics 16PP303, and
McAir A3818, A5232, and A5690. For the Enhanced
Mini-ACE RT mode, there is programmable flexibility
enabling the RT to be configured to fulfill any set of system
requirements. This includes the capability to meet the
MIL-STD-1553A response time requirement of 2 to 5
µs,
and multiple options for mode code subaddresses, mode
codes, RT status word, and RT BIT word.
RT global circular buffer
Like the ACE and Mini-ACE, the Enhanced
Mini-ACE offers a programmable choice of single buffer
mode, double buffer mode, or circular buffer mode,
programmable on an individual subaddress basis. The
Enhanced Mini-ACE RT architecture provides an additional
option, in that it allows for a variable sized global circular
buffer. The Enhanced Mini-ACE RT allows for a mix of
single buffered, double buffered, and individually circular
buffered subaddresses, along with the use of a global
circular buffer for any arbitrary group of subaddresses.
In the global circular buffer mode, the data for multiple
receive subaddresses is stored in the same circular buffer
data structure. The size of the global data structure may be
programmed to be either a single message; or a circular
buffer of 128, 256, 512, 1024, 2048, 4096, or 8192 words.
Individual receive subaddresses may be mapped to the
global circular buffer by means of their respective
subaddress control word.
The global circular buffer option provides a highly efficient
method for storing received message data. It allows for
frequently used subaddresses to be mapped to individual
data blocks, while also providing a method for
asynchronously received messages to infrequently used
subaddresses to be logged to a common area.
RT and MT: Interrupt status queue
The Enhanced Mini-ACE RT and MT (monitor
terminal) mode include capability to use an interrupt
status queue. As illustrated in Figure 5, this provides a
chronological history of interrupt generating events and
conditions. The interrupt status queue is 64 words deep,
providing the capability to store entries for up to 32
messages. These events and conditions include both
message-related and non-message-related occurrences.
Each message or non-message condition or event that
causes an interrupt results in a two-word entry to be added
to the queue. The first word of the entry is the interrupt
vector; this word indicates which interrupt event(s)/
condition(s) caused the interrupt. The second word is a
parameter. For a message-related interrupt, the parameter
is a pointer to the first word of the RT or MT stack
descriptor (the Block Status Word). For a non-message
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
