IDTCSP5993
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PROGRAMMABLE SKEW
PLL CLOCK DRIVER
TURBOCLOCK™
FEATURES:
•
•
•
•
•
•
•
•
3 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 6.25MHz to 100MHz
2x, 4x, 1/2, and 1/4 outputs
5V with TTL outputs
3 skew grades:
CSP5993-2: t
SKEW0
<250ps
CSP5993-5: t
SKEW0
<500ps
CSP5993-7: t
SKEW0
<750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
46mA I
OL
high drive outputs
Low Jitter: <200ps peak-to-peak
Outputs drive 50Ω terminated lines
Available in QSOP Package
IDTCSP5993
DESCRIPTION:
The CSP5993 is a high fanout PLL based clock driver intended for
high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or
lag the REF input signal. The CSP5993 has six programmable skew
outputs and two zero skew outputs. Skew is controlled by 3-level input
signals that may be hard-wired to appropriate HIGH-MID-LOW levels.
•
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
G ND/sOE
Skew
Select
3
3
1F1:0
V
CCQ
/PE
Skew
Select
REF
PLL
FB
3
FS
Skew
Select
3
3
3F1:0
3
3
2F1:0
1Q
0
1Q
1
2Q
0
2Q
1
3Q
0
3Q
1
4Q
0
4Q
1
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
1
c
2000
Integrated Device Technology, Inc.
FEBRUARY 2000
DSC-5811/-
IDTCSP5993
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
REF
V
CCQ
FS
3F
0
3F
1
V
CC Q
/PE
V
CCN
4Q
1
4Q
0
GND
3Q
1
3Q
0
V
CCN
FB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SO28-9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
TEST
2F
1
2F
0
GND/sOE
1F
1
1F
0
V
CCN
1Q
0
1Q
1
GND
GND
2Q
0
2Q
1
ABSOLUTE MAXIMUM RATINGS
Symbol
V
I
T
STG
Rating
Supply Voltage to Ground
DC Input Voltage
Maximum Power Dissipation (T
A
= 85°C)
Storage Temperature Range
Max.
–0.5 to +7
–0.5 to +7
0.66
(1)
Unit
V
V
W
–65°C to +150°C °C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= 25° C, f = 1MHz, V
IN
= 0V)
Parameter
C
IN
Description
Input Capacitance
Typ.
4
Max.
6
Unit
pF
NOTE:
1. Capacitance applies to all inputs except TEST, FS, and nF1:0.
QSOP
TOP VIEW
PIN DESCRIPTION
Pin Name
REF
FB
TEST
(1)
GND/
sOE
(1)
Type
IN
IN
IN
IN
Reference Clock Input
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control
Summary Table) remain in effect. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (Except 3Q
0
and 3Q
1
) in a LOW state - 3Q
0
and 3Q
1
may be used
as the feedback signal to maintain phase lock. When TEST is held at MID level and GND/sOE is HIGH, the nF[
1:0
] pins act as
output disable controls for individual banks when nF[
1:0
] = LL. Set GND/sOE LOW for normal operation.
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
3-level inputs for selecting 1 of 9 skew taps or frequency functions.
Selects appropriate oscillator circuit based on anticipated frequency range. (See PLL Programmable Skew Range.)
Four banks of two outputs with programmable skew (1Q:3Q), and 4Q output has fixed zero skew outputs.
Power supply for output buffers
Power supply for phase locked loop and other internal circuitry
Ground
Description
V
CCQ
/PE
nF[
1:0
]
FS
nQ[
1:0
]
V
CCN
V
CCQ
GND
IN
IN
IN
OUT
PWR
PWR
PWR
NOTE:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[
1:0
] = LL functioning as an output disable control for individual output banks.
Skew selections remain in effect unless nF[
1:0
] = LL.
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit t
U
which is of the
order of a nanosecond (see PLL Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF
1:0
control pins. In order
2
to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF
1:0
control pins.
IDTCSP5993
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
EXTERNAL FEEDBACK
By providing external feedback, the CSP5993 gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
FS = LOW
Timing Unit Calculation (t
U
)
VCO Frequency Range (F
NOM
)
(1,2)
Skew Adjustment Range
(3)
Max Adjustment:
±9.09ns
±49º
±14%
Example 1, F
NOM
= 25MHz
Example 2, F
NOM
= 30MHz
Example 3, F
NOM
= 40MHz
Example 4, F
NOM
= 50MHz
Example 5, F
NOM
= 80MHz
t
U
= 0.91ns
t
U
= 0.76ns
—
—
—
±9.23ns
±83º
±23%
t
U
= 1.54ns
t
U
= 1.28ns
t
U
= 0.96ns
t
U
= 0.77ns
—
±9.38ns
±135º
±37%
—
—
t
U
= 1.56ns
t
U
= 1.25ns
t
U
= 0.78ns
ns
Phase Degrees
% of Cycle Time
1/(44 x F
NOM
)
25 to 35MHz
FS = MID
1/(26 x F
NOM
)
35 to 60MHz
FS = HIGH
1/(16 x F
NOM
)
60 to 100 MHz
(4)
Comments
NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the ap-
propriate FS value based on input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is lowest.
2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always ap-
pears at 1Q
1:0
, 2Q
1:0
, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will
be the same as the VCO when the output connected to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency
when the part is configured for a frequency multiplication by using a divided output as the FB input.
3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will
be greater. For example if a 4t
U
skewed output is used for feedback, all other outputs will be skewed –4t
U
in addition to whatever skew value is programmed
for those outputs. ‘Max adjustment’ range applies to output pair 3 where ± 6t
U
skew adjustment is possible and at the lowest F
NOM
value.
4. The maximum REF Clock Input Frequency is 85MHz. Use Q/2 or Q/4 as feedback and use the Control Summary Table for output pairs explicitly
for output frequency to 100MHz.
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0
LL
(1)
LM
LH
ML
MM
MH
HL
HM
HH
NOTE:
1. LL disables outputs if TEST = MID and GND/sOE = HIGH.
Skew (Pair #1, #2)
–4t
U
–3t
U
–2t
U
–1t
U
Zero Skew
1t
U
2t
U
3t
U
4t
U
Skew (Pair #3)
Divide by 2
–6t
U
–4t
U
–2t
U
Zero Skew
2t
U
4t
U
6t
U
Divide by 4
3
IDTCSP5993
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING RANGE
CSP5993-5, -7
(Industrial)
Symbol
Vcc
T
A
Description
Power Supply Voltage
Ambient Operating Temperature
Min.
4.5
-40
Max.
5.5
+85
Min.
4.75
0
CSP5993-2
(Commercial)
Max.
5.25
+70
Unit
V
°C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IN
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
(1)
Input MID Voltage
(1)
Input LOW Voltage
(1)
Input Leakage Current
(REF, FB Inputs Only)
3-Level Input DC Current (TEST, FS, nF1:0)
Input Pull-Up Current (V
CCQ
/PE)
Input Pull-Down Current (GND/sOE)
Output HIGH Voltage
Output LOW Voltage
Output Short Circuit Current
(2)
Conditions
Guaranteed Logic HIGH (REF, FB Inputs Only)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
V
IN
= V
CC
or GND
V
CC
= Max.
V
IN
= V
CC
V
IN
= V
CC
/2
V
IN
= GND
I
PU
I
PD
V
OH
V
OL
I
OS
V
CC
= Max., V
IN
= GND
V
CC
= Max., V
IN
= V
CC
V
CC
= Min., I
OH
=
−16mA
V
CC
= Min., I
OH
=
−40mA
V
CC
= Min., I
OL
= 46mA
V
CC
= Max., V
O
= GND
Min.
2
—
V
CC
−1
V
CC
/2−0.5
—
—
HIGH Level
MID Level
LOW Level
—
—
—
—
—
2.4
—
—
—
Max.
—
0.8
—
V
CC
/2+0.5
1
±5
±200
±50
±200
±100
±100
—
—
0.45
−
250
µA
µA
V
V
V
mA
µA
Unit
V
V
V
V
V
µA
I
3
NOTES:
1. These inputs are normally wired to V
CC
, GND, or unconnected. Internal termination resistors bias unconnected inputs to V
CC
/2. If these inputs are
switched, the function and timing of the outputs may be glitched, and the PLL may require an additional t
LOCK
time before all datasheet limits are
achieved.
2. This is to be measured at 25°C with 10:1 duty cycle, one output at a time, and one second maximum.
POWER SUPPLY CHARACTERISTICS
Symbol
I
CCQ
∆I
CC
I
CCD
I
TOT
Parameter
Quiescent Power Supply Current
Power Supply Current per Input HIGH
Dynamic Power Supply Current per Output
Total Power Supply Current
Test Conditions
V
CC
= Max., TEST = MID, REF = LOW,
GND/sOE = LOW, All outputs unloaded
V
CC
= Max., V
IN
= 3.4V
V
CC
= Max., C
L
= 0pF
V
CC
= 5V, F
REF
= 20MHz, C
L
= 240pF
(1)
V
CC
= 5V, F
REF
= 33MHz, C
L
= 240pF
(1)
V
CC
= 5V, F
REF
= 66MHz, C
L
= 240pF
(1)
NOTE:
1. For eight outputs, each loaded with 30pF.
Typ.
10
0.4
100
43
63
117
Max.
40
1.5
160
—
—
—
Unit
mA
mA
µA/MHz
mA
mA
mA
4
IDTCSP5993
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
t
PWC
D
H
R
EF
Description
(1)
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
Reference Clock Input
Min.
—
3
10
10
Max.
10
—
90
85
Unit
ns/V
ns
%
MHz
NOTE:
1. Where pulse width implied by D
H
is less than t
PWC
limit, t
PWC
limit applies.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
CSP5993-2
Symbol
F
NOM
t
RPWH
t
RPWL
t
U
t
SKEWPR
t
SKEW0
t
SKEW1
t
SKEW2
t
SKEW3
t
DEV
t
PD
t
ODCV
t
PWH
t
PWL
t
ORISE
t
OFALL
t
LOCK
t
JR
Parameter
VCO Frequency Range
REF Pulse Width HIGH
(1)
REF Pulse Width LOW
(1)
Programmable Skew Time Unit
Zero Output Matched-Pair Skew (xQ
0
, xQ
1
)
(1,2, 3)
Zero Output Skew (All Outputs) C
L
= 0pF
(1, 4)
Output Skew
(Rise-Rise, Fall-Fall, Same Class Outputs)
(1, 3)
Output Skew
(Rise-Fall, Nominal, Divided-Divided)
(1, 5)
Output Skew
(Rise-Rise, Fall-Fall, Different Class Outputs)
(1, 5)
Device-to-Device Skew
( 1,2, 6)
REF Input to FB Propagation Delay
( 1,8)
Output Duty Cycle Variation from 50%
(1)
Output HIGH Time Deviation from 50%
(1,9)
Output LOW Time Deviation from 50%
(1,10)
Output Rise Time
(1)
Output Fall Time
(1)
PLL Lock Time
(7)
Cycle-to-Cycle Output Jitter
RMS
Peak-to-Peak
—
—
—
—
—
—
−0.25
−1.2
—
—
0.15
0.15
—
—
—
0.05
0.1
0.25
0.5
0.25
—
0
0
—
—
1
1
—
—
—
0.2
0.25
0.5
01.2
0.5
0.75
0.25
1.2
2
2.5
1.5
1.5
0.5
25
200
Min.
3
3
Typ.
—
—
CSP5993-5
CSP5993-7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
See PLL Programmable Skew Range and Resolution Table
—
—
3
3
—
—
—
—
—
—
−0.5
−1.2
—
—
0.15
0.15
—
—
—
—
—
0.1
0.25
0.6
0.5
0.5
—
0
0
—
—
1
1
—
—
—
—
—
0.25
0.5
0.7
1.2
0.7
1.25
0.5
1.2
2.5
3
1.5
1.5
0.5
25
200
3
3
—
—
—
—
—
—
−0.7
−1.2
—
—
0.15
0.15
—
—
—
—
—
0.1
0.3
0.6
0.5
0.7
—
0
0
—
—
1.5
1.5
—
—
—
—
—
0.25
0.75
1
1.5
1.2
1.65
0.7
1.2
3
3.5
2.5
2.5
0.5
25
200
See Skew Selection Table for Output Pairs
NOTES:
1. All timing tolerances apply for F
NOM
> 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same t
U
delay has been selected when all are
loaded with the specified load.
3. t
SKEWPR
is the skew between a pair of outputs (xQ
0
and xQ
1
) when all eight outputs are selected for 0t
U
.
4. t
SKEW0
is the skew between outputs when they are selected for 0t
U
.
5. There are two classes of outputs: Nominal (multiple of t
U
delay) and Divided (3Qx only in Divide-by-2 or Divide-by-4 mode).
6. t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
CC
, ambient temperature, air flow, etc.)
7. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal operating
limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t
PD
is within specified limits.
8. t
PD
is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.
9. Measured at 2V.
10. Measured at 0.8V.
11. Refer to Input Timing Requirements table for more detail.
5
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