RoHS Compliant
2GB ECC DDR3 SDRAM 1.35V UDIMM
Product Specifications
April 7, 2016
Version 1.2
Apacer Technology Inc.
1F., No.32, Zhongcheng Rd., Tucheng Dist., New Taipei City 236, Taiwan
Tel: +886-2-2267-8000
www.apacer.com
Fax: +886-2-2267-2261
Table of Contents
General Description ....................................................................................................... 2
Ordering Information ..................................................................................................... 2
Key Parameters .............................................................................................................. 2
Specifications: ................................................................................................................ 3
Features: ......................................................................................................................... 4
Pin Assignments ............................................................................................................. 5
Pin Descriptions ............................................................................................................. 7
Functional Block Diagram ............................................................................................. 8
Absolute Maximum Ratings .......................................................................................... 9
DRAM Component Operating Temperature Range..................................................... 10
Operating Conditions ................................................................................................... 11
Mechanical Drawing .................................................................................................... 12
©Apacer Technology Inc.
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General Description
Apacer
78.A1GG3.4020C
is a 256M x 72 DDR3 SDRAM (Synchronous
DRAM) ECC DIMM. This high-density memory module consists of 9 pieces
256M x 8 bits with 8 banks DDR3 synchronous DRAMs in BGA packages and
a 2K EEPROM. The module is a 240-pins dual in-line memory module and is
intended for mounting into a connector socket. Decoupling capacitors are
mounted on the printed circuit board for each DDR3 SDRAM. The following
provides general specifications of this module.
Ordering Information
Part Number
78.A1GG3.4020C
Bandwidth
12.8 GB/sec
Speed Grade
1600Mbps
Max Frequency
800 MHz
CAS Latency
CL11
Density
2GB
Organization
256M x 72
Component
256M x8*9
Rank
1
Key Parameters
MT/s
Grade
DDR3-1066
-CL7
1.875
7
13.125
13.125
37.5
50.625
7-7-7
DDR3-1333
-CL9
1.5
9
13.5
13.5
36
49.5
9-9-9
DDR3-1600
-CL11
1.25
11
13.75
13.75
35
48.75
11-11-11
Unit
tCK (min)
CAS latency
tRCD (min)
tRP (min)
tRAS (min)
tRC (min)
CL-tRCD-tRP
ns
tCK
ns
ns
ns
ns
tCK
©Apacer Technology Inc.
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Specifications:
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Support ECC error detection and correction
On-DIMM thermal sensor : Yes
Organization: 256 words x 72 bits, 1 rank
Integrating 9 pieces of 2G bits DDR3 SDRAM sealed FBGA
Package: 240-pin socket type dual in-line memory module (ECC DIMM)
PCB: height 30.0 mm, lead pitch 1.0 mm (pin), lead-free (RoHS compliant)
Power supply VDD: 1.35V (+0.1V ~ -0.067V)
Backward compatible to VDD = VDDQ = 1.5V ± 0.075V
-Supports DDR3L devices to be backward compatible in 1.5V applications
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Serial Presence Detect (SPD)
Eight Internal banks for concurrent operation (components)
Interface: SSTL_13
Burst lengths (BL): 8 and 4 with Burst Chop (BC)
CAS Latency (CL): 6, 7, 8, 9, 10, 11
CAS Write Latency (CWL): 5, 6, 7, 8
Supports auto pre-charge option for each burst access
Supports auto-refresh/self-refresh
Refresh cycles: 7.8
㎲
at 0℃≦ TC
≦
+85℃
PCB: 30µ gold finger
©Apacer Technology Inc.
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Features:
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Double-date-rate architecture: 2 data transfers per clock cycle
The high-speed data transfer is realized by the 8 bits prefetch pipelined
architecture
Bi-directional differential data strobe (DQS and /DQS) is transmitted /
received with data for capturing data at the receiver
DQS is edge-aligned with data for READs; center aligned with data for
WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK transitions
Data mask (DM) for writing data
Posted /CAS by programmable additive latency for enhanced command
and data bus efficiency
On-Die-Termination (ODT) for improved signal quality: Synchronous
ODT/Dynamic ODT/Asynchronous ODT
Multi-Purpose Register (MPR) for temperature read out
ZQ calibration for DQ drive and ODT
Programmable Partial Array Self-Refresh (PASR)
/Reset pin for power-up sequence and reset function
SRT range: normal/extended, auto/manual self-refresh
Programmable output driver impedance control
Commands entered at each positive clock input, while data and data mask
are referenced to both edges of DQS
©Apacer Technology Inc.
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