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IDT74GTLP306PG

产品描述Bus Transceiver, GTLP Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, TSSOP-24
产品类别逻辑   
文件大小53KB,共7页
制造商IDT (Integrated Device Technology)
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IDT74GTLP306PG概述

Bus Transceiver, GTLP Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, TSSOP-24

IDT74GTLP306PG规格参数

参数名称属性值
是否无铅含铅
是否Rohs认证不符合
厂商名称IDT (Integrated Device Technology)
零件包装代码TSSOP
包装说明TSSOP-24
针数24
Reach Compliance Codenot_compliant
Is SamacsysN
控制类型COMMON CONTROL
计数方向BIDIRECTIONAL
系列GTLP
JESD-30 代码R-PDSO-G24
JESD-609代码e0
长度7.8 mm
逻辑集成电路类型BUS TRANSCEIVER
最大I(ol)0.05 A
湿度敏感等级1
位数8
功能数量1
端口数量2
端子数量24
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP24,.25
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度)NOT SPECIFIED
电源3.3 V
Prop。Delay @ Nom-Sup8.3 ns
传播延迟(tpd)8.3 ns
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.465 V
最小供电电压 (Vsup)3.135 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Tin/Lead (Sn85Pb15)
端子形式GULL WING
端子节距0.65 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
翻译GTL/P & LVTTL
宽度4.4 mm
Base Number Matches1

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IDT74GTLP306
8-BIT LVTTL/GTLP BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
8-BIT LVTTL/GTLP
BUS TRANSCEIVER
IDT74GTLP306
FEATURES:
Bidirectional interface between GTLP and LVTTL logic levels
Edge Rate Control Circuit reduces output noise
V
REF
pin provides reference voltage for receiver threshold
CMOS technology for low power dissipation
Special PVT Compensation circuitry to provide consistent perfor-
mance over variations of process, supply voltage, and temperature
5V tolerant inputs on LVTTL ports
Bus-Hold to eliminate the need for external pull-up resistors for
unused inputs to A-Port
Power up/down and power-off high-impedance for live insertion
TTL-compatible Driver and Control inputs
High Output source/sink ±24mA on A-Port pins
Flow-through architecture optimizes system layout
Open drain on GTLP to support wired OR connection
ESD performance of >2000V
Available in TSSOP package
DESCRIPTION:
The GTLP306 is an 8-bit bus transceiver. It provides signal level
translation, from LVTTL to GTLP, for applications requiring a high-speed
interface between cards operating at LVTTL logic levels and back-planes
operating at GTLP logic levels. GTLP provides reduced output swing
(<1V), reduced input threshold levels, and output edge-rate control to
minimize signal setting times. The GTLP306 is a derivative of the Gunning
Transceiver Logic (GTL) JEDEC standard JESD8-3 and incorporates
internal edge-rate control, which is process, voltage, and temperature
(PVT) compensated.
The GTLP306 combines a transceiver function with an LVTTL to GTLP
translation. Data polarity is non-inverting, and the data flow direction is
controlled by the T/R pin. The outputs are enabled to allow data through
the device when
OE
is low. Otherwise, both A and B are placed in a high-
impedance state.
GTLP output low voltage is less than 0.5V. The output high is 1.5V, and
the receiver threshold is 1V.
FUNCTIONAL BLOCK DIAGRAM
T/R
OE
A0 (LVTTL I/O)
B0 (GTLP I/O)
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2002 Integrated Device Technology, Inc.
MAY 2002
DSC-5978/9

 
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