Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Capacitor Array, C0G Dielectric, 10 – 200 VDC
(Commercial & Automotive Grade)
Overview
KEMET’s Ceramic Chip Capacitor Array in C0G dielectric is an
advanced passive technology where multiple capacitor elements
are integrated into one common monolithic structure. Array
technology promotes reduced placement costs and increased
throughput. This is achieved by alternatively placing one device
rather than two or four discrete devices. Use of capacitor arrays
also saves board space which translates into increased board
density and more functions per board. Arrays consume only
a portion of the space required for standard chips resulting in
savings in inventory and pick/place machine positions.
KEMET’s C0G dielectric features a 125°C maximum operating
temperature and is considered “stable.”The Electronics
Industries Alliance (EIA) characterizes C0G dielectric as a Class
I material. Components of this classification are temperature
compensating and are suited for resonant circuit applications or
those where Q and stability of capacitance characteristics are
required. C0G exhibits no change in capacitance with respect to
time and voltage and boasts a negligible change in capacitance
with reference to ambient temperature. Capacitance change is
limited to ±30 ppm/ºC from -55°C to +125°C.
KEMET automotive grade array capacitors meet the demanding
Automotive Electronics Council's AEC–Q200 qualification
requirements.
Benefits
•
•
•
•
•
-55°C to +125°C operating temperature range
Saves both circuit board and inventory space
Reduces placement costs and increases throughput
RoHS Compliant
EIA 0508 (2-element) and 0612 (4-element) case sizes
Ordering Information
CA
Ceramic
Array
06
4
C
104
Capacitance
Code (pF)
2 Significant
Digits + Number
of Zeros
K
Capacitance
Tolerance
J = ±5%
K = ±10%
M = ±20%
4
Voltage
G
Dielectric
A
C
TU
Packaging/Grade
(C-Spec)
3
Blank = Bulk
TU = 7" Reel
Unmarked
AUTO =
Automotive Grade
Case Size Number of
Specification/
(L" x W")
1
Capacitors
Series
05 = 0508
06 = 0612
2=2
4=4
C = Standard
X = Flexible
Termination
Failure Rate/ Termination
Design
Finish
2
A = N/A
C = 100%
Matte Sn
L = SnPb (5%
minimum)
8 = 10 V G = C0G
4 = 16 V
3 = 25 V
5 = 50 V
1 = 100 V
2 = 200 V
All previous reference to metric case dimension "1632" has been replaced with an inch standard reference of "0612". Please reference all new designs using the
"0612" nomenclature. "CA064" replaces "C1632" in the ordering code.
2
Additional termination finish options may be available. Contact KEMET for details.
2,3
SnPb termination finish option is not available on automotive grade product.
3
Additional reeling or packaging options may be available. Contact KEMET for details.
1
One world. One KEMET
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com
C1016_C0G_ARRAY_SMD • 5/30/2013
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Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Capacitor Array, C0G Dielectric, 10 – 200 VDC, (Commercial & Automotive Grade)
Dimensions – Millimeters (Inches)
EIA
Size
Code
0508
0612
Metric
Size
Code
1220
1632
L
Length
1.30 (0.051)
±0.15 (0.006)
1.60 (0.063)
±0.20 (0.008)
W
Width
2.10 (0.083)
±0.15 (0.006)
3.20 (0.126)
±0.20 (0.008)
BW
Bandwidth
0.53 (0.021)
±0.08 (0.003)
0.40 (0.016)
±0.20 (0.008)
BL
Bandlength
0.30 (0.012)
±0.20 (0.008)
0.30 (0.012)
±0.20 (0.008)
T
Thickness
See Table 2 for
Thickness
P
Pitch
1.00 (0.039)
±0.10 (0.004)
0.80 (0.031)
±0.10 (0.004)
P/2
Reference
0.50 (0.020)
±0.10 (0.004)
0.40 (0.031)
±0.05 (0.002)
Benefits cont'd
•
•
•
•
•
DC voltage ratings of 10 V, 16 V, 25 V, 50 V, 100 V, and 200 V
Capacitance offerings ranging from 10 pF to 2,200 pF
Available capacitance tolerances of ±5%, ±10%, and ±20%
Non-polar device, minimizing installation concerns
100% pure matte tin-plated termination finish allowing for
excellent solderability
• SnPb termination finish option available upon request (5%
minimum)
• Flexible termination option available upon request
• Commercial and Automotive (AEC–Q200) grades available
Applications
Typical applications include those that can benefit from board area savings, cost savings and overall volumetric reduction such as
telecommunications, computers, handheld devices and automotive.
Qualification/Certification
Commercial Grade products are subject to internal qualification. Details regarding test methods and conditions are referenced in
Table 4, Performance & Reliability.
Automotive Grade products meet or exceed the requirements outlined by the Automotive Electronics Council. Details regarding test
methods and conditions are referenced in document AEC–Q200, Stress Test Qualification for Passive Components. For additional
information regarding the Automotive Electronics Council and AEC–Q200, please visit their website at www.aecouncil.com.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com
C1016_C0G_ARRAY_SMD • 5/30/2013
2
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Capacitor Array, C0G Dielectric, 10 – 200 VDC, (Commercial & Automotive Grade)
Environmental Compliance
Pb-Free and RoHS Compliant (excluding SnPb termination finish option).
Electrical Parameters/Characteristics
Item
Operating Temperature Range
Capacitance Change with Reference to +25°C and 0 VDC Applied (TCC)
Aging Rate (Maximum % Capacitance Loss/Decade Hour)
Dielectric Withstanding Voltage (DWV)
Dissipation Factor (DF) Maximum Limit @ 25ºC
Insulation Resistance (IR) Limit @ 25°C
-55°C to +125°C
±30 ppm/ºC
0%
250% of rated voltage
(5 ±1 seconds and charge/discharge not exceeding 50 mA)
0.1%
1,000 megohm microfarads or 100 GΩ
(Rated voltage applied for 120 ±5 seconds @ 25°C)
Parameters/Characteristics
To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits.
Capacitance and dissipation factor (DF) measured under the following conditions:
1 MHz ±100 kHz and 1.0 Vrms ±0.2 V if capacitance ≤ 1,000 pF
1 kHz ±50 Hz and 1.0 Vrms ±0.2 V if capacitance > 1,000 pF
Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known as
Automatic Level Control (ALC). The ALC feature should be switched to "ON."
Post Environmental Limits
High Temperature Life, Biased Humidity, Moisture Resistance
Dielectric
C0G
Rated DC
Voltage
All
Capacitance
Value
All
Dissipation Factor
(Maximum %)
0.5
Capacitance
Shift
Insulation
Resistance
0.3% or ±0.25 pF 10% of Initial Limit
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com
C1016_C0G_ARRAY_SMD • 5/30/2013
3
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Capacitor Array, C0G Dielectric, 10 – 200 VDC, (Commercial & Automotive Grade)
Table 1 – Capacitance Range/Selection Waterfall (0508 – 0612 Case Sizes)
Series
Capacitance
10 pF
12 pF
15 pF
18 pF
22 pF
27 pF
33 pF
39 pF
47 pF
56 pF
68 pF
82 pF
100 pF
120 pF
150 pF
180 pF
220 pF
270 pF
330 pF
390 pF
470 pF
560 pF
680 pF
820 pF
1,000 pF
1,100 pF
1,200 pF
1,300 pF
1,500 pF
1,600 pF
1,800 pF
2,000 pF
2,200 pF
C0508 (CA052C 2-Cap Case Size)
8
10
4
16
3
5
1
8
C0612 (CA064C 4-Cap Case Size)
4
3
5
1
100
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
Capacitance
Code
100
120
150
180
220
270
330
390
470
560
680
820
101
121
151
181
221
271
331
391
471
561
681
821
102
112
122
132
152
162
182
202
222
Voltage Code
Voltage DC
Capacitance
Tolerance
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
2
200
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
25
50
100
10
16
25
50
Product Availability and Chip Thickness Codes
See Table 2 for Chip Thickness Dimensions
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
MA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
PA
Capacitance
Capacitance
Code
Voltage DC
Voltage Code
10
8
16
4
25
3
C0508
50
5
100
1
10
8
16
4
25
3
50
5
100
1
200
2
Series
C0612
KEMET reserves the right to substitute product with an improved temperature characteristic, tighter capacitance tolerance and/or higher voltage capability within
the same form factor (configuration and dimensions).
These products are protected under US Patents 7,172,985 and 7,670,981, other patents pending, and any foreign counterparts.
Table 2 – Chip Thickness/Packaging Quantities
Thickness
Code
PA
MA
Case
Size
0508
0612
Thickness ±
Range (mm)
0.80 ± 0.10
0.80 ± 0.10
Paper Quantity
7" Reel
0
0
Plastic Quantity
7" Reel
4,000
4,000
13" Reel
0
0
13" Reel
10,000
10,000
Package quantity based on finished chip thickness specifications.
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com
C1016_C0G_ARRAY_SMD • 5/30/2013
4
Roll Over for
Order Info.
Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs)
Capacitor Array, C0G Dielectric, 10 – 200 VDC, (Commercial & Automotive Grade)
Table 3 – Chip Capacitor Array Land Pattern Design Recommendations per IPC-7351
EIA SIZE
CODE
0508/CA052
0612/CA064
METRIC
SIZE
CODE
1220
1632
Density Level A:
Maximum (Most) Land
Protrusion (mm)
C
1.60
1.80
Y
1.00
1.10
X
0.55
0.50
P
1.00
0.80
V1
3.50
3.90
V2
3.30
4.40
C
1.50
1.80
Density Level B:
Median (Nominal) Land
Protrusion (mm)
Y
0.90
0.95
X
0.50
0.50
P
1.00
0.80
V1
2.90
3.30
V2
2.80
3.90
C
1.40
1.70
Density Level C:
Minimum (Least) Land
Protrusion (mm)
Y
0.75
0.85
X
0.45
0.40
P
1.00
0.80
V1
2.40
2.80
V2
2.50
3.60
Density Level A:
For low-density product applications. Provides a wider process window for reflow solder processes.
Density Level B:
For products with a moderate level of component density. Provides a robust solder attachment condition for reflow solder processes.
Density Level C:
For high component density product applications. Before adapting the minimum land pattern variations the user should perform qualification
testing based on the conditions outlined in IPC Standard 7351 (IPC–7351).
V2
P
X
V1
C
Y
Grid Placement Courtyard
Soldering Process
Recommended Soldering Technique:
• Solder reflow only
Recommended Soldering Profile:
• KEMET recommends following the guidelines outlined in IPC/JEDEC J–STD–020
© KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 (864) 963-6300 • www.kemet.com
C1016_C0G_ARRAY_SMD • 5/30/2013
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