AURIX™ Product Naming
Brand
Device
Primary
Option
Secondary Option
SA
K
–
TC
2 7
5
T
Series
Package Class
Architecture
Feature Package
Infineon product
identifier
Temperature
range
TriCore
Core Architecture
– 64
F
200
N
Frequency
N
W
F
L
S
Q
Temp. Range
K
-40°C - +125°C
L
-40°C - +150°C
Package Class
9 LFBGA-516
8 BGA-416
7 LFBGA-292
5 QFP-176
4 QFP-144
3 QFP-100
2 QFP-80
0 Bare Die
Core Architecture
T Triple Core
D Dual Core
S Single Core
L Single Core
with Lockstep
Feature packages
- Production Dev., No HSM
P Prod. Dev., HSM enabled
E Emulation Dev., no HSM
F Emulation Dev., HSM enabled
A ADAS enhanced, HSM enabled
B ADAS enhanced, no HSM
X Feature ext., HSM enabled
Y Feature ext., no HSM
C Customer specific
Flash size code
8
16
24
32
40
64
96
128
0.5 MB
1 MB
1.5 MB
2 MB
2.5 MB
4 MB
6 MB
8 MB
Secondary Feature
code
CAN FD ISO 11898-1
Memory Type
LQFP 0.5mm pitch
TQFP 0.4mm pitch
BGA 1.0 mm pitch
LFBGA 0.8mm pitch
Fusion Quad QFP
0.5 mm pitch
Secondary
Feature Type
Memory Size
2015-06
Copyright © Infineon Technologies AG 2015. All rights reserved.
2
Naming Convention for
TriCore®
Family
Example: SAK-TC1796-256F150E
Automotive families:
1: Industry
2: Body
3: Safety
7: Powertrain
Code memory size:
n*8k Bytes
e.g. 64: 64*8k=512k
Component
specific
Temp.
Range
Code
Code
Size
Mem.
Type
CPU
Freq.
Prefix
Type
Variation
Package
SA
B
F
H
K
TC1
y
xx
ED
##
L
F
40
66
80
150
300
H
H
N
E
Variation:
ED = emulation device
Other = blank
B = 0/ 70 °C
F = -40/ 85 °C
H = -40/ 110°C
K = -40/ 125°C
Example: SAK-TC1796-256F150E
L = Flashless
F = Flash
H = Quad flat pack
HL = L-QFP
HM = M-QFP
HT = T-QFP
E = P-BGA
EL = P-LFBGA
ET = P-TFBGA
EB =P-LBGA
U = flip-chip, bare die
Page 2
Copyright © Infineon Technologies AG 2013. All rights reserved.
Naming Convention for
XMC4000
Family
Example: XMC4500–F144K1024 AC
Family
Core
Feature
Package
Pins
Temp.
Flash [kB]
Step
XMC
4
5
0
4
2
0
2
4
1
8
E
F
Q
144
100
64
48
K
X
F
1024
768
512
256
128
64
AA
AB
AC
Silicon Version
AA = 01
AB = 02
AC = 03
K = -40° to 125°C
X = -40° to 105°C
F = -40° to 85°C
E = LFBGA | F = LQFP | Q = VQFN
0 = Full Featured < ….. > 8 = Feature Subset
1 = Baseline < ….. > 5 = High-End
ARM® Cortex™-M4
with built in DSP, SPFPU, DMA and MPU
XMC := Industrial Microcontroller Family based on ARM® Cortex™-M Processors
Copyright © Infineon Technologies AG 2013. All rights reserved.
Page 3
Naming Convention for
XMC1000
Family
Example: XMC1302-T038X0200 AA
Family
Core
Feature
Package
Pins
Temp.
Flash [kB]
Step
XMC
1
3
2
2 0 1
1
0
Q
T
40
38
28
24
16
X
F
200
128
64
32
16
8
AA
Silicon Version
AA = 01
X = -40° to 105°C
F = -40° to 85°C
Q = VQFN | T = TSSOP
2 = Full Featured < ….. > 0 = Feature Subset
1 = Baseline < ….. > 3 = High-End
ARM® Cortex™-M0
XMC := Industrial Microcontroller Family based on ARM® Cortex™-M Processors
Copyright © Infineon Technologies AG 2013. All rights reserved.
Page 4
Naming Convention for
16-bit
Family
Example: SAF-XC161CJ-14F20F
Core:
XC16 = C166S V2
C16 = C166
Code memory size:
n*8k Bytes
e.g. 4: 4*8k=32k
(blank for ROMless)
CPU Speed:
n*1 MHz
(blank for
Standard speed)
Prefix
Sub-Family
Type
SA
F
K
A
XC16
1
CJ
#
R
F
E
L
#
F
M
E
Key Features
Temp. Range:
F = -40/ 85 °C
K = -40/ 125°C
A = -40/ 140°C
Package:
F = P-TQFP
M = P-MQFP
E = P-BGA
Code Memory Type:
R = ROM
F = Flash
E = OTP
L = ROMless
Page 5
Copyright © Infineon Technologies AG 2013. All rights reserved.
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