IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
COMMERCIAL TEMPERATURE RANGE
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
(WITH 3-STATE)
NOT RECOMMENDED FOR NEW DESIGNS
IDT74FCT388915T
70/100/133/150
NRND
FEATURES:
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
• Max. output frequency: 150MHz
• Pin and function compatible with FCT88915T, MC88915T
• 5 non-inverting outputs, one inverting output, one 2x output,
one ÷2 output; all outputs are TTL-compatible
• 3-State outputs
• Duty cycle distortion < 500ps (max.)
• 32/–16mA drive at CMOS output voltage levels
• V
CC
= 3.3V ± 0.3V
• Inputs can be driven by 3.3V or 5V components
• Available in 28 pin PLCC and SSOP packages
•
NOT RECOMMENDED FOR NEW DESIGNS
DESCRIPTION:
The FCT388915T uses phase-lock loop technology to lock the fre-
quency and phase of outputs to the input reference clock. It provides low
skew clock distribution for high performance PCs and workstations. One of
the outputs is fed back to the PLL at the FEEDBACK input resulting in
essentially zero delay across the device. The PLL consists of the phase/
frequency detector, charge pump, loop filter and VCO. The VCO is
designed for a 2Q operating frequency range of 40MHz to f2Q Max.
The FCT388915T provides 8 outputs, the
Q5
output is inverted from the
Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs at half the
Q frequency.
The FREQ_SEL control provides an additional ÷ 2 option in the output
path. PLL _EN allows bypassing of the PLL, which is useful in static test
modes. When PLL_EN is low, SYNC input may be used as a test clock. In
this test mode, the input frequency is not limited to the specified range and
the polarity of outputs is complementary to that in normal operation (PLL_EN
= 1). The LOCK output attains logic HIGH when the PLL is in steady-state
phase and frequency lock. When OE/RST is low, all the outputs are put in
high impedance state and registers at Q,
Q
and Q/2 outputs are reset.
The FCT388915T requires one external loop filter component as
recommended in Figure 3.
FUNCTIONAL BLOCK DIAGRAM
FEED BAC K
Voltage
Controlled
Oscilator
LF
REF_SEL
PLL_EN
0
1
M ux
( 1)
1M
0
u
x
D
Q
LOCK
SYNC (0)
SYNC (1)
0M
u
1x
Phase/Freq.
Detector
Charge Pum p
2Q
Q0
Divide
-By-2
FREQ_SEL
OE/RST
( 2)
CP R Q
D
CP
R
Q
R
Q
Q
Q1
D
CP
Q2
D
CP R
D
CP
R
Q3
Q
Q4
D
CP R
D
CP R
Q
Q5
Q
Q/2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
MAY 2013
DSC-4243/7
© 2013 Integrated Device Technology, Inc.
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE/RST
GND
V
CC
V
CC
Q5
Q4
GND
Q5
V
CC
OE/RST
FEEDBACK
REF_SEL
SYNC(0)
V
CC
(AN)
LF
GND(AN)
SYNC(1)
FREQ_SEL
GND
Q0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Q4
V
CC
2Q
Q/2
GND
Q3
V
CC
Q2
GND
LOCK
PLL_EN
GND
Q1
V
CC
SYNC(0)
V
CC
(AN)
LF
GND(AN)
SYNC(1)
7
8
9
10
11
FEEDBK
REF_SEL
5
6
4
3
2
1
28
27
26
25
24
23
22
21
20
19
Q/2
GND
Q3
V
CC
Q2
GND
LOCK
12
FREQ_SEL
13
GND
14
Q0
15
V
CC
16
Q1
17
GND
18
PLL_EN
SSOP
TOP VIEW
PLCC
TOP VIEW
PIN DESCRIPTION
Pin Name
SYNC(0)
SYNC(1)
REF_SEL
FREQ_SEL
FEEDBACK
LF
Q0-Q4
Q5
2Q
Q/2
LOCK
OE/RST
PLL_EN
I/O
I
I
I
I
I
I
O
O
O
O
O
I
I
Reference clock input
Reference clock input
Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram)
Selects between ÷ 1 and ÷ 2 frequency options (refer to functional block diagram)
Feedback input to phase detector
Input for external loop filter connection
Clock output
Inverted clock output
Clock output (2 x Q frequency)
Clock output (Q frequency ÷ 2)
Indicates phase lock has been achieved (HIGH when locked)
Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are enabled. When LOW, outputs are in
HIGH impedance.
Disables phase-lock for low frequency testing (refer to functional block diagram)
Description
2
2Q
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
V
TERM
(3)
V
TERM
(4)
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +4.6
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +60
Unit
V
V
V
°C
mA
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
4.5
5.5
Max.
6
8
Unit
pF
pF
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Outputs and I/O terminals.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 3.3V ± 0.3V
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
V
OH
V
OL
V
H
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(4)
(3-State Output Pins)
Clamp Diode Voltage
Output Drive Current
Output Drive Current
Output HIGH Voltage
Output LOW Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min., I
IN
= –18mA
V
CC
= Min., V
IN
= V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= Min., V
IN
= V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= Min
V
CC
= Min
—
V
CC
= Max.,V
IN
= GND or V
CC
(Test Mode)
I
OH
= –16mA
I
OL
= 32mA
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.
V
I
= 5.5V
V
I
= GND
V
I
= V
CC
V
I
= GND
Min.
2
—
—
—
—
—
—
–36
50
2.4
(4)
—
—
—
Typ.
(2)
—
—
—
—
—
—
–0.7
—
—
3.3
0.3
100
2
Max.
5.5
0.8
±1
±1
±1
±1
–1.2
—
—
—
0.5
—
6
V
mA
mA
V
V
mV
µA
Unit
V
V
µA
µA
µA
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. V
OH
= V
CC
- 0.6V at rated current.
3
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
C
PD
I
C
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Power Dissipation Capacitance
Total Power Supply Current
(6)
V
CC
= Max.
V
IN
= V
CC
–2.1V
(3)
V
CC
= Max.
All Outputs Open
50% Duty Cycle
V
CC
= Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. All bits loaded with 15pF
V
CC
= Max.
PLL_EN = 1, LOCK = 1, FEEDBACK = Q4
SYNC frequency = 50MHz. All bits loaded with 50Ω Thevenin
termination and 20pF
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Per TTL driven input. All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+ DI
CC
D
H
N
T
+ I
CCD
(f) + I
LOAD
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
ΔI
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f = 2Q Frequency
I
LOAD
= Dynamic Current due to load.
Test Conditions
(1)
V
IN
= V
CC
–0.6V
(3)
V
IN
= V
CC
V
IN
= GND
Min.
—
—
—
—
Typ.
(2)
2
0.2
15
30
Max.
30
0.3
25
60
Unit
µA
mA/
MHz
pF
mA
—
90
120
mA
SYNCH INPUT TIMING REQUIRMENTS
Symbol
T
RISE/FALL
Parameter
Rise/Fall Times, SYNC inputs
(0.8V to 2V)
Frequency Input Frequency, SYNC Inputs
Duty Cycle Input Duty Cycle, SYNC Inputs
10
(1)
25%
2Q fmax
75%
MHz
—
Min.
—
Max.
3
Unit
ns
OUTPUT FREQUENCY SPECIFICATIONS
Max.
(2)
Symbol
f2Q
fQ
fQ/2
Parameter
Operating frequency 2Q Output
Operating frequency Q0-Q4,
Q5
Outputs
Operating frequency Q/2 Output
Min.
40
20
10
70
70
35
17.5
100
100
50
25
133
(3)
133
66.7
33.3
150
(3)
150
75
37.5
Unit
MHz
MHz
MHz
NOTES:
1. Note 7 in "General AC Specification Notes" and Figure 3 describes this specification and its actual limits depending on the feedback connection.
2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded.
3. At this frequency, 2Q cannot be used as feedback.
4
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
RISE/FALL
All Outputs
t
PULSE WIDTH (3)
Q,
Q,
Q/2 outputs
(3)
t
PULSE WIDTH
2Q Output
(3)
t
PD
t
SKEW
r
(rising)
(3,4)
t
SKEW
f
(falling)
(3,4)
t
SKEW
all
(3,4)
t
LOCK(6)
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Rise/Fall Time
(between 0.8V and 2V)
Output Pulse Width
Q0-Q4,
Q5,
Q/2, @ 1.5V
Output Pulse Width
2Q @ 1.5V
SYNC input to FEEDBACK delay
Output to Output Skew between outputs 2Q, Q0-Q4,
Q/2 (rising edges only)
Output to Output Skew
between outputs Q0-Q4 (falling edges only)
Output to Output Skew
2Q, Q/2, Q0-Q4 rising,
Q5
falling
Time required to acquire Phase-Lock from time
SYNC input signal is received
Output Enable Time
OE/RST (LOW-to-HIGH) to Q, 2Q, Q/2,
Q
Output Disable Time
OE/RST (HIGH-to-LOW) to Q, 2Q, Q/2,
Q
3
(2)
14
ns
3
(2)
14
ns
1
(2)
10
ms
—
800
ps
—
250
ps
Load = 50Ω to V
CC
/2, C
L
= 20pF
0.1µF from LF to Analog GND
(5)
Load = 50Ω to V
CC
/2, C
L
= 20pF
—
600
ps
+0.1
+1.3
ns
0.5t
CYCLE
– 1
(5)
0.5t
CYCLE
+ 1
(5)
ns
Load = 50Ω to V
CC
/2, C
L
= 20pF
0.5t
CYCLE
– 0.8
(5)
0.5t
CYCLE
+ 0.8
(5)
ns
Condition
(1)
Load = 50Ω to V
CC
/2, C
L
= 20pF
Min.
0.2
(2)
Max.
2
Unit
ns
SYNC-FEEDBACK
(3)
(measured at SYNC0 or 1 and FEEDBACK input pins)
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.
5. t
CYCLE
= 1/frequency at which each output (Q,
Q,
Q/2 or 2Q) is expected to run.
6. With V
CC
fully powered-on and an output properly connected to the FEEDBACK pin, t
LOCK
Max. is with C1 = 0.1µF, t
LOCK
Min. is with C1 = 0.01µF. (Where C1 is loop filter
capacitor shown in Figure 2).
7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable
SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW.
Also it is possible to feed back the
Q5
output, thus creating a 180° phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC
frequency range for each possible configuration.
FREQ_SEL
Level
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Feedback
Output
Q/2
Any Q (Q0-Q4)
Q5
2X_Q
Q/2
Any Q (Q0-Q4)
Q5
2X_Q
Allowable SYNC Input
Frequency Range (MHZ)
10 to (2x_Q f
MAX
Spec)/4
20 to (2x_Q f
MAX
Spec)/2
20 to (2x_Q f
MAX
Spec)/2
40 to (2x_Q f
MAX
Spec)
5 to (2x_Q f
MAX
Spec)/8
10 to (2x_Q f
MAX
Spec)/4
10 to (2x_Q f
MAX
Spec)/4
20 to (2x_Q f
MAX
Spec)/2
Corresponding 2Q Output
Frequency Range
40 to (2Q f
MAX
Spec)
40 to (2Q f
MAX
Spec)
40 to (2Q f
MAX
Spec)
40 to (2Q f
MAX
Spec)
20 to (2Q f
MAX
Spec)/2
20 to (2Q f
MAX
Spec)/2
20 to (2Q f
MAX
Spec)/2
20 to (2Q f
MAX
Spec)/2
Phase Relationship of the Q Outputs
to Rising SYNC Edge
0°
0°
180°
0°
0°
0°
180°
0°
5
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