PF1550
Power management integrated circuit (PMIC) for low power
application processors
Rev. 5 — 10 June 2019
Product data sheet
1
General description
The PF1550 is a power management integrated circuit (PMIC) designed specifically for
use with i.MX processors on low-power portable, smart wearable and Internet-of-Things
(IoT) applications. It is also capable of providing full power solution to i.MX 7ULP, i.MX
6SL, 6UL, 6ULL, and 6SX processors.
With three high-efficiency buck converter, three linear regulators, RTC supply, and
battery linear charger, the PF1550 can provide power for a complete battery-powered
system, including application processors, memory, and system peripherals.
1.1 Features and benefits
This section summarizes the PF1550 features:
•
Input voltage range to PMIC VBUSIN pin via USB bus or AC adapter: 4.1 V to 6.0 V
•
Buck converters:
–
SW1, 1.0 A; 0.6 V to 1.3875 V in 12.5 mV steps, or 1.1 V to 3.3 V in variable steps
–
SW2, 1.0 A; 0.6 V to 1.3875 V in 12.5 mV steps, or 1.1 V to 3.3 V in variable steps
–
SW3, 1.0 A; 1.8 V to 3.3 V in 100 mV steps
–
Soft start
–
Quiescent current 1.0 μA in ULP mode with light load
–
Peak efficiency > 90 %
–
Dynamic voltage scaling on SW1 and SW2
–
Modes: forced PWM quasi-fixed frequency mode, adaptive variable-frequency mode
–
Programmable output voltage, current limit, and soft start
•
LDO regulators
–
LDO1, 0.75 V to 1.5 V/1.8 to 3.3 V, 300 mA with load switch mode
–
LDO2, 1.8 V to 3.3 V, 400 mA
–
LDO3, 0.75 V to 1.5 V/1.8 V to 3.3 V, 300 mA with load switch mode
–
Quiescent current < 1.5 μA in Low-power mode
–
Programmable output voltage
–
Soft start and ramp
–
Current limit protection
•
Battery charger
–
Supports single-cell Lithium Ion/Lithium Polymer batteries
–
Linear charging (10 mA to 1500 mA input limit)
–
Up to 6.5 V input operating range
–
VSYS regulator can withstand transient and DC inputs from 0 V up to +22 V
–
Programmable charge voltage (3.5 V to 4.44 V)
–
Programmable charge current (100 mA to 1000 mA)
–
Programmable charge termination current (5.0 mA to 50 mA)
NXP Semiconductors
Power management integrated circuit (PMIC) for low power application processors
–
Integrated 50 mΩ battery isolation MOSFET for operation with no/low battery
–
Battery supplement mode
–
Battery discharge overcurrent protection, up to 3.0 A
–
USB_PHY low dropout linear regulator
–
Programmable LED driver (status indicator)
–
JEITA-compliant battery temp sensing and charger control
–
Key charging parameters can be configured and permanently stored in OTP
2
–
I C Control Interface permitting processor control and event detection
LDO/switch supply
–
RTC supply VSNVS 3.0 V, 2.0 mA
–
Battery backed memory including coin cell charger
DDR memory reference voltage, VREFDDR, 0.5 V to 0.9 V, 10 mA
OTP (One time programmable) memory for device configuration
–
User programmable start-up sequence, timing, soft-start, and power-down sequence
–
Programmable regulator output voltages and charger parameters
2
I C interface
User programmable Standby, Sleep/Low-power, and Off (REGS_DISABLE) modes
Ambient temperature range −40 °C to 105 °C
PF1550
•
•
•
•
•
•
1.2 Applications
•
•
•
•
•
•
•
Smart mobile/wearable devices
Low-power IoT applications
Wireless game controllers
Embedded monitoring systems
Home automation
POS
E-Read
PF1550
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 5 — 10 June 2019
2 / 150
NXP Semiconductors
Power management integrated circuit (PMIC) for low power application processors
PF1550
2
Application diagram
PF1550
VREFDDR
DDR memory
DDR memory Interface
SW2
SW1
GPS
MIPI
Processor ARM core
Processor real-time
SOC/GPU
FLASH
NAND - NOR
interfaces
Low-power application
processor
LDO1
SW3
LDO2
LDO3
VSNVS
SD/MMC/
NAND memory
WiFi
Bluetooth
SNVS_IN
External AMP
microphones
speakers
Audio codec
Control signals
I
2
C communication
Li-cell
charger
Parallel control / GPIO
I
2
C communication
Sensors
Coin cell
Mini-USB
linear charger
USB_PHY
Mini-USB connector
aaa-023872
Figure 1. Application diagram
PF1550
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 5 — 10 June 2019
3 / 150
NXP Semiconductors
Power management integrated circuit (PMIC) for low power application processors
PF1550
2.1 Functional block diagram
PF1550 functional block diagram
BUCK1
(0.6 V to 1.3875 V, 1.0 A, DVS;
1.1 V to 3.3 V, 1.0 A, no DVS)
BUCK2
(0.6 V to 1.3875 V, 1.0 A, DVS;
1.1 V to 3.3 V, 1.0 A, no DVS)
Logic and Control
I
2
C/processor interface/
regulator control/
OTP
(flexible configuration)
Linear Li-ion battery charger
(22 V surge, power path,
100 mA to 1000 mA charging current)
LDO1
(0.75 V to 3.3 V, 300 mA)
BUCK3
(1.8 V to 3.3 V, no DVS)
LDO2
(1.8 V to 3.3 V, 400 mA)
VSNVS (RTC supply)
(3.0 V, 2.0 mA)
LDO3
(0.75 V to 3.3 V, 300 mA)
DDR voltage reference
(V
INREFDDR
/2, 10 mA)
aaa-023873
Figure 2. Functional block diagram
PF1550
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 5 — 10 June 2019
4 / 150
NXP Semiconductors
Power management integrated circuit (PMIC) for low power application processors
PF1550
2.2 Internal block diagram
RESETBMCU
VDDOTP
PWRON
ONKEY
VDDIO
CHGB
INTB
SDA
SCL
WDI
PF1550 analog core
(reference and bias current)
SW1FB
SW1IN
SW1LX
EPAD
OTP memory
EA and
driver
SW1 DVS
and misc
reference
VCORE
LDO
PF1550 digital core
and state machine
VCORE
VDIG
LDO
VDIG
coin cell
charger
SW2FB
SW2IN
SW2LX
EPAD
EA and
driver
Watchdog
timer
VSNVS
32 kHz clock
LICELL
VSNVS
VSYS
SW2 DVS
and misc
reference
16 MHz clock
VBUSIN
SW3FB
SW3IN
SW3LX
EPAD
EA and
driver
SW3
and misc
reference
LDO1
LDO2
LDO3
INT2P7
LDO
USBPHY
LDO
USBPHY
INT2P7
VBATT
Thermistor
monitor
THM
VREFDDR
divide input by 2
LDO1OUT
LDO2OUT
VINREFDDR
VREFDDR
Digital signal(s)
Analog reference(s)
16 MHz clock / derivative
32 kHz clock / derivative
LDO3OUT
LDO1IN
LDO2IN
LDO3IN
aaa-023874
Figure 3. Internal block diagram
3
Orderable parts
The PF1550 is available only with preprogrammed configurations. These preprogrammed
devices are identified using the program code from
Table 1,
which also list the associated
NXP reference designs where applicable. Details of the OTP programming for each
device can be found in
Table 85.
PF1550
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Product data sheet
Rev. 5 — 10 June 2019
5 / 150
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
