NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMXRT1050CEC
Rev. 1.3, 03/2019
MIMXRT1051DVL6A
MIMXRT1051DVL6B
MIMXRT1051DVJ6B
MIMXRT1052DVL6A
MIMXRT1052DVL6B
MIMXRT1052DVJ6B
i.MX RT1050 Crossover
Processors Data Sheet
for Consumer Products
Package Information
Plastic Package
196-pin MAPBGA, 10 x 10 mm, 0.65 mm pitch
196-pin MAPBGA, 12 x 12 mm, 0.8 mm pitch
Ordering Information
See
Table 1 on page 5
1
i.MX RT1050 introduction
1. i.MX RT1050 introduction . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 5
2. Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1. Special signal considerations . . . . . . . . . . . . . . . 15
3.2. Recommended connections for unused analog
interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 18
4.2. System power and clocks . . . . . . . . . . . . . . . . . . 25
4.3. I/O parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.4. System modules . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.5. External memory interface . . . . . . . . . . . . . . . . . 41
4.6. Display and graphics . . . . . . . . . . . . . . . . . . . . . . 51
4.7. Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.8. Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.9. Communication interfaces . . . . . . . . . . . . . . . . . . 64
4.10. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 79
5.1. Boot mode configuration pins . . . . . . . . . . . . . . . 79
5.2. Boot device interface allocation . . . . . . . . . . . . . . 79
6. Package information and contact assignments . . . . . . . 84
6.1. 10 x 10 mm package information . . . . . . . . . . . . 84
6.2. 12 x 12 mm package information . . . . . . . . . . . . 96
7. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
The i.MX RT1050 is a new processor family featuring
NXP’s advanced implementation of the Arm
Cortex®-M7 core, which operates at speeds up to 600
MHz to provide high CPU performance and best
real-time response.
The i.MX RT1050 processor has 512 KB on-chip RAM,
which can be flexibly configured as TCM or
general-purpose on-chip RAM. The i.MX RT1050
integrates advanced power management module with
DCDC and LDO that reduces complexity of external
power supply and simplifies power sequencing. The
i.MX RT1050 also provides various memory interfaces,
including SDRAM, RAW NAND FLASH, NOR
FLASH, SD/eMMC, Quad SPI, and a wide range of
other interfaces for connecting peripherals, such as
WLAN, Bluetooth™, GPS, displays, and camera
sensors. The i.MX RT1050 also has rich audio and video
features, including LCD display, basic 2D graphics,
camera interface, SPDIF, and I2S audio interface. The
NXP reserves the right to change the production detail specifications as may be required
to permit improvements in the design of its products.
i.MX RT1050 introduction
i.MX RT1050 has analog interfaces, such as ADC, ACMP, and TSC.
The i.MX RT1050 is specifically useful for applications such as:
• Industrial Human Machine Interfaces (HMI)
• Motor Control
• Home Appliance
1.1
Features
The i.MX RT1050 processors are based on Arm Cortex-M7 MPCore™ Platform, which has the
following features:
• Supports single Arm Cortex-M7 MPCore with:
— 32 KB L1 Instruction Cache
— 32 KB L1 Data Cache
— Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture
— Support the Armv7-M Thumb instruction set
• Integrated MPU, up to 16 individual protection regions
• Up to 512 KB I-TCM and D-TCM in total
• Frequency of 600 MHz
• Cortex M7 CoreSight™ components integration for debug
• Frequency of the core, as per
Table 10, "Operating ranges," on page 20.
The SoC-level memory system consists of the following additional components:
— Boot ROM (96 KB)
— On-chip RAM (512 KB)
– Configurable RAM size up to 512 KB shared with M7 TCM
• External memory interfaces:
— 8/16-bit SDRAM, up to SDRAM-166
— 8/16-bit SLC NAND FLASH, with ECC handled in software
— SD/eMMC
— SPI NOR FLASH
— Parallel NOR FLASH with XIP support
— Single/Dual channel Quad SPI FLASH with XIP support
• Timers and PWMs:
— Two General Programmable Timers (GPT)
– 4-channel generic 32-bit resolution timer
– Each support standard capture and compare operation
— Four Periodical Interrupt Timer (PIT)
– Generic 16-bit resolution timer
– Periodical interrupt generation
i.MX RT1050 Crossover Processors Data Sheet for Consumer Products, Rev. 1.3, 03/2019
2
NXP Semiconductors
i.MX RT1050 introduction
— Four Quad Timers (QTimer)
– 4-channel generic 16-bit resolution timer for each
– Each support standard capture and compare operation
– Quadrature decoder integrated
— Four FlexPWMs
– Up to 8 individual PWM channels for each
– 16-bit resolution PWM suitable for Motor Control applications
— Four Quadrature Encoder/Decoders
Each i.MX RT1050 processor enables the following interfaces to external devices (some of them are
muxed and not available simultaneously):
• Display Interface:
— Parallel RGB LCD interface
– Support 8/16/24 bit interface
– Support up to 1366 x 768 WXGA resolution
– Support Index color with 256 entry x 24 bit color LUT
– Smart LCD display with 8/16-bit MPU/8080 interface
• Audio:
— S/PDIF input and output
— Three synchronous audio interface (SAI) modules supporting I2S, AC97, TDM, and
codec/DSP interfaces
— MQS interface for medium quality audio via GPIO pads
• Generic 2D graphics engine:
— BitBlit
— Flexible image composition options—alpha, chroma key
— Image rotation (90
, 180
, 270
)
— Porter-Daff operation
— Image size
— Color space conversion
— Multiple pixel format support (RGB, YUV444, YUV422, YUV420, YUV400)
— Standard 2D-DMA operation
• Camera sensors:
— Support 24-bit, 16-bit, and 8-bit CSI input
• Connectivity:
— Two USB 2.0 OTG controllers with integrated PHY interfaces
— Two Ultra Secure Digital Host Controller (uSDHC) interfaces
– MMC 4.5 compliance with HS200 support up to 200 MB/sec
– SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec
i.MX RT1050 Crossover Processors Data Sheet for Consumer Products, Rev. 1.3, 03/2019
NXP Semiconductors
3
i.MX RT1050 introduction
•
– Support for SDXC (extended capacity)
— One 10/100 M Ethernet controller with support for IEEE1588
— Eight universal asynchronous receiver/transmitter (UARTs) modules
— Four I2C modules
— Four SPI modules
— Two FlexCAN modules
GPIO and Pin Multiplexing:
— General-purpose input/output (GPIO) modules with interrupt capability
— Input/output multiplexing controller (IOMUXC) to provide centralized pad control
— Two FlexIOs
The i.MX RT1050 processors integrate advanced power management unit and controllers:
• Full PMIC integration. On-chip DCDC and LDO
• Temperature sensor with programmable trip points
• GPC hardware power management controller
The i.MX RT1050 processors support the following system debug:
• Arm CoreSight debug and trace architecture
• Trace Port Interface Unit (TPIU) to support off-chip real-time trace
• Support for 5-pin (JTAG) and SWD debug interfaces selected by eFuse
Security functions are enabled and accelerated by the following hardware:
• High Assurance Boot (HAB)
• Data Co-Processor (DCP):
— AES-128, ECB, and CBC mode
— SHA-1 and SHA-256
— CRC-32
• Bus Encryption Engine (BEE)
— AES-128, ECB, and CTR mode
— On-the-fly QSPI Flash decryption
• True random number generation (TRNG)
• Secure Non-Volatile Storage (SNVS)
— Secure real-time clock (RTC)
— Zero Master Key (ZMK)
• Secure JTAG Controller (SJC)
NOTE
The actual feature set depends on the part numbers as described in
Table 1.
Functions such as display and camera interfaces, connectivity interfaces,
and security features are not offered on all derivatives.
i.MX RT1050 Crossover Processors Data Sheet for Consumer Products, Rev. 1.3, 03/2019
4
NXP Semiconductors
i.MX RT1050 introduction
1.2
Ordering information
Table 1. Ordering information
Table 1
provides examples of orderable part numbers covered by this Data Sheet.
Junction
Temperature T
j
(C)
0 to +95
Part Number
MIMXRT1051DVL6A
MIMXRT1051DVL6B
Features
Package
• 600 MHz, commercial
grade for general
purpose with
MPU/FPU
• eDMA
• Boot ROM (96 KB)
• On-chip RAM (512
KB)
• SEMC
• GPT x2
• 4-channel PIT
• PWM x4
• ENC x4
• WDOG x4
• No LCD/CSI/PXP
• SPDIF x1
• SAI x3
• MQS x1
• USB OTG x2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
eMMC 4.5/SD 3.0 x2
10 x 10 mm, 0.65 mm pitch,
196-pin MAPBGA
SPI x4
Ethernet
UART x8
I
2
C x4
FlexSPI
CAN x2
FlexIO x2
127 GPIOs
HAB/DCP/BEE
TRNG
SNVS
SJC
ADC x2
ACMP x4
TSC
DCDC
Temperature sensor
GPC hardware power
management
controller
eMMC 4.5/SD 3.0 x2
12 x 12 mm, 0.8 mm pitch,
196-pin MAPBGA
SPI x4
Ethernet
UART x8
I
2
C x4
FlexSPI
CAN x2
FlexIO x2
127 GPIOs
HAB/DCP/BEE
TRNG
SNVS
SJC
ADC x2
ACMP x4
TSC
DCDC
Temperature sensor
GPC hardware power
management
controller
MIMXRT1051DVJ6B
• 600 MHz, commercial
grade for general
purpose with
MPU/FPU
• eDMA
• Boot ROM (96 KB)
• On-chip RAM (512
KB)
• SEMC
• GPT x2
• 4-channel PIT
• PWM x4
• ENC x4
• WDOG x4
• No LCD/CSI/PXP
• SPDIF x1
• SAI x3
• MQS x1
• USB OTG x2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0 to +95
i.MX RT1050 Crossover Processors Data Sheet for Consumer Products, Rev. 1.3, 03/2019
NXP Semiconductors
5
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