Si5397/96 Data Sheet
Dual/Quad DSPLL
™
Any-Frequency, Any-Output Jitter Attenua-
tors
The Si5397 is a high-performance, 8-output jitter-attenuating clock multiplier which inte-
grates four any-frequency DSPLLs for applications that require maximum integration
and independent timing paths. The Si5396 is a 4-output, dual DSPLL version in a
smaller package. Each DSPLL has access to any of the four inputs and can provide
low jitter clocks on any of the device outputs. Based on 4
th
generation DSPLL technolo-
gy, these devices provide any-frequency conversion with typical jitter performance of
95 fs. Each DSPLL supports independent free-run, holdover modes of operation, as
well as automatic and hitless input clock switching. The Si5397/96 is programmable via
a serial interface with in-circuit programmable non-volatile memory so that it always
powers up in a known configuration. Programming the Si5397/96 is easy with Silicon
Labs'
ClockBuilder Pro
software. Factory pre-programmed devices are also available.
KEY FEATURES
• Each DSPLL generates any output
frequency from any input frequency
• Four or two DSPLLs to synchronize to
multiple time domains
• Ultra-low phase jitter of 95 fs rms
• Enhanced hitless switching minimizes
output phase transients
• Input frequency range:
• Differential: 8 kHz to 750 MHz
• LVCMOS: 8 kHz to 250 MHz
• Output frequency range:
• Differential: 100 Hz to 720 MHz
• LVCMOS: 100 Hz 250 MHz
• Status Monitoring
• Option for integrated reference
• Si5397: 4 input, 8 output, 64-QFN 9×9 mm
• Si5396: 4 input, 4 output, 44-QFN 7×7 mm
• Drop-in compatible with Si5347/46
Applications
• OTN Muxponders and Transponders
• 10/40/100/400GbE
• Synchronous Ethernet (ITU-T G.8262)
• 10/25/100G Carrier Ethernet switches
• Broadcast video
Integrated
Reference*
IN0
4 Input
Clocks
IN1
IN2
IN3
÷FRAC
÷FRAC
÷FRAC
÷FRAC
DSPLL A
DSPLL B
DSPLL C
DSPLL D
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
Si5396A/B
Si5397C/D
Si5397A/B
Status Flags
I
2
C / SPI
Status Monitor
Control
NVM
*Future product (J/K/L/M). Si539x A/B/C/D grades have external reference (XTAL or XO)
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This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Preliminary Rev. 0.96
Si5397/96 Data Sheet
Feature List
1. Feature List
The Si5397/96 features are listed below:
• Generates any combination of output frequencies from any in-
put frequency
• Integrated reference (J/K/L/M) - Future Product
• Ultra-low phase jitter of 95 fs rms
• Four or two DSPLLs to synchronize to multiple inputs
• Input frequency range:
• Differential: 8 kHz to 750 MHz
• LVCMOS: 8 kHz to 250 MHz
• Output frequency range:
• Differential: up to 720 MHz
• LVCMOS: up to 250 MHz
• Flexible crosspoints route any input to any output clock
• Programmable jitter attenuation bandwidth per DSPLL: 0.1 Hz
to 4 kHz
• Highly configurable outputs compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL with programmable signal ampli-
tude
• Status monitoring (LOS, OOF, LOL)
• Enhanced hitless switching minimizes output phase transients
for 8 kHz, 19.44 MHz, 25 MHz, and other input frequencies
• Drop-in compatible with Si5347/46
•
•
•
•
•
•
Locks to gapped clock inputs
Automatic free-run and holdover modes
Fastlock feature for low nominal bandwidths
Independent Frequency-on-the-fly for each DSPLL
DCO mode: as low as 0.01 ppb steps per DSPLL
Core voltage:
• V
DD
: 1.8 V ±5%
• V
DDA
: 3.3 V ±5%
• Independent output clock supply pins: 3.3, 2.5, or 1.8 V
• Serial interface: I
2
C or SPI
• In-circuit programmable with non-volatile OTP memory
• ClockBuilder
™
Pro software tool simplifies device configuration
• Si5397A/B: Quad DSPLL, 4 input, 8 output, 64-QFN 9×9 mm
• Si5397C/D: Quad DSPLL, 4 input, 4 output, 64-QFN 9×9 mm
• Si5396: Dual DSPLL, 4 input, 4 output, 44-QFN 7×7 mm
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
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Preliminary Rev. 0.96 | 2
Si5397/96 Data Sheet
Related Documents
2. Related Documents
Table 2.1. Related Documentation and Software
Document/Resource
Description/URL
https://www.silabs.com/documents/login/reference-manuals/
si5397-96-family.pdf
The reference manual is intended to be used in conjunction with
this data sheet, which contains more detailed explanations about
the operation of the device.
https://www.silabs.com/documents/public/reference-manuals/
si534x-8x-9x-recommended-crystals-rm.pdf
https://www.silabs.com/documents/public/user-guides/ug353-
si5397evb.pdf
https://www.silabs.com/documents/public/application-notes/
an1151-using-si539x.pdf
https://www.silabs.com/documents/public/application-notes/
an1155-differences-between-si5342-47-and-si5392-97.pdf
http://www.silabs.com/Si5397-96FAQ
http://www.silabs.com/quality
https://www.silabs.com/products/development-tools/timing/
clock#highperformance
https://www.silabs.com/products/development-tools/software/
clockbuilder-pro-software
Si5397/96 Family Reference Manual
Crystal Reference Manual
UG353: Si5397-EVB User Guide
AN1151: Using the Si539x in 56G SerDes Applications
AN1155: Differences between Si5342-47 and Si5392-97
Frequently Asked Questions
Quality and Reliability
Development Kits
ClockBuilder Pro (CBPro) Software
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Preliminary Rev. 0.96 | 3
Si5397/96 Data Sheet
Ordering Guide
3. Ordering Guide
Table 3.1. Si5397/96 Ordering Guide
Output Clock
Package
Frequency Range
Temp Range
Ref
Ordering Part Number
Si5397
Si5397A-A-GM
1,2
Si5397B-A-GM
1,2
Si5397C-A-GM
1,2
Si5397D-A-GM
1,2
Si5396
Si5396A-A-GM
1,2
Si5396B-A-GM
1,2
Si5397A-A-EVB
Number Of
DSPLLs
Number of
Outputs
8
4
4
0.0001 to 720 MHz
0.0001 to 350 MHz
0.0001 to 720 MHz
0.0001 to 350 MHz
64-QFN 9x9 mm
–40 to 85 °C
External
2
—
4
—
0.0001 to 720 MHz
0.0001 to 350 MHz
—
44-QFN 7x7 mm
Evaluation Board
—
External
Notes:
1. Add an R at the end of the device part number to denote tape and reel ordering options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by the ClockBuilder Pro software.
Part number format is: Si5397A-Axxxxx-GM or Si5396A-Axxxxx-GM, where “xxxxx” is a unique numerical sequence representing
the pre-programmed configuration.
Figure 3.1. Ordering Part Number Fields
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Preliminary Rev. 0.96 | 4
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Frequency Configuration .
4.2 DSPLL Loop Bandwidth
4.3 Fastlock Feature .
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. 7
. 7
. 7
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8
8
8
9
9
9
9
4.4 Modes of Operation . . . . . .
4.4.1 Initialization and Reset . . .
4.4.2 Free-run Mode . . . . .
4.4.3 Lock Acquisition Mode . . .
4.4.4 Locked Mode . . . . . .
4.4.5 Holdover Mode . . . . .
4.4.6 Frequency-on-the-Fly (FOTF)
4.6 External Reference (XA/XB) .
.
.
4.5 Digitally-Controlled Oscillator (DCO) Mode .
4.7 Inputs (IN0, IN1, IN2, IN3) . . . . . . .
4.7.1 Input Selection . . . . . . . .
4.7.2 Manual Input Selection . . . . . .
4.7.3 Automatic Input Selection . . . . .
4.7.4 Hitless Input Switching . . . . . .
4.7.5 Frequency Ramped Input Switching .
4.7.6 Glitchless Input Switching . . . . .
4.7.7 Typical Hitless Switching Scenarios .
4.7.8 Synchronizing to Gapped Input Clocks
4.8 Fault Monitoring . . . .
4.8.1 Input LOS Detection.
4.8.2 XA/XB LOS Detection
4.8.3 OOF Detection . .
4.8.4 LOL Detection . . .
4.8.5 Interrupt Pin (INTRb)
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.10
.10
.10
.11
.11
.11
.11
.11
.11
.12
.13
.14
.14
.14
.15
.16
.17
.17
.17
.17
.17
.17
.17
.17
.18
.18
.18
.18
4.9 Outputs . . . . . . . . . . . . . . . . . . . . .
4.9.1 Output Crosspoint . . . . . . . . . . . . . . .
4.9.2 Output Signal Format . . . . . . . . . . . . . .
4.9.3 Programmable Common Mode Voltage For Differential Outputs
4.9.4 LVCMOS Output Impedance Selection . . . . . . . .
4.9.5 LVCMOS Output Signal Swing . . . . . . . . . . .
4.9.6 LVCMOS Output Polarity . . . . . . . . . . . . .
4.9.7 Output Enable/Disable . . . . . . . . . . . . . .
4.9.8 Output Disable During LOL . . . . . . . . . . . .
4.9.9 Output Disable During XAXB_LOS . . . . . . . . . .
4.9.10 Output Driver State When Disabled . . . . . . . . .
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Preliminary Rev. 0.96 | 5
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