LPC2292/2294
16/32-bit ARM microcontrollers; 256 kB ISP/IAP flash with
CAN, 10-bit ADC and external memory interface
Rev. 8 — 8 June 2011
Product data sheet
1. General description
The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with
real-time emulation and embedded trace support, together with 256 kB of embedded
high-speed flash memory. A 128-bit wide memory interface and a unique accelerator
architecture enable 32-bit code execution at the maximum clock rate. For critical code
size applications, the alternative 16-bit Thumb mode reduces code by more than 30 %
with minimal performance penalty.
With their 144-pin package, low power consumption, various 32-bit timers, 8-channel
10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine
external interrupt pins these microcontrollers are particularly suitable for automotive and
industrial control applications as well as medical systems and fault-tolerant maintenance
buses. The number of available GPIOs ranges from 76 (with external memory) through
112 (single-chip). With a wide range of additional serial communications interfaces, they
are also suited for communication gateways and protocol converters as well as many
other general-purpose applications.
Remark:
Throughout the data sheet, the term LPC2292/2294 will apply to devices with
and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from
other devices only when necessary.
2. Features and benefits
2.1 Key features brought by LPC2292/2294/01 devices
Fast GPIO ports enable port pin toggling up to 3.5 times faster than the original device.
They also allow for a port pin to be read at any time regardless of its function.
Dedicated result registers for ADC(s) reduce interrupt overhead. The ADC pads are
5 V tolerant when configured for digital I/O function(s).
UART0/1 include fractional baud rate generator, auto-bauding capabilities and
handshake flow-control fully implemented in hardware.
Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
SPI programmable data length and master mode enhancement.
Diversified Code Read Protection (CRP) enables different security levels to be
implemented. This feature is available in LPC2292/2294/00 devices as well.
General purpose timers can operate as external event counters.
2.2 Key features common for all devices
16/32-bit ARM7TDMI-S microcontroller in a LQFP144 package.
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
16 kB on-chip static RAM and 256 kB on-chip flash program memory. 128-bit wide
interface/accelerator enables high-speed 60 MHz operation.
In-System Programming/In-Application Programming (ISP/IAP) via on-chip bootloader
software. Single flash sector or full chip erase in 400 ms and programming of 256 B in
1 ms.
EmbeddedICE-RT and Embedded Trace interfaces offer real-time debugging with the
on-chip RealMonitor software as well as high-speed real-time tracing of instruction
execution.
Two/four (LPC2292/2294) interconnected CAN interfaces with advanced acceptance
filters. Additional serial interfaces include two UARTs (16C550), Fast I
2
C-bus
(400 kbit/s) and two SPIs.
Eight channel 10-bit ADC with conversion time as low as 2.44
s.
Two 32-bit timers (with four capture and four compare channels), PWM unit (six
outputs), Real-Time Clock (RTC), and watchdog.
Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses.
Configurable external memory interface with up to four banks, each up to 16 MB and
8/16/32-bit data width.
Up to 112 general purpose I/O pins (5 V tolerant). Up to nine edge/level sensitive
external interrupt pins available.
60 MHz maximum CPU clock available from programmable on-chip PLL with settling
time of 100
s.
The on-chip crystal oscillator should have an operating range of 1 MHz to 25 MHz.
Power saving modes include Idle and Power-down.
Processor wake-up from Power-down mode via external interrupt.
Individual enable/disable of peripheral functions for power optimization.
Dual power supply:
CPU operating voltage range of 1.65 V to 1.95 V (1.8 V
0.15 V).
I/O power supply range of 3.0 V to 3.6 V (3.3 V
10 %) with 5 V tolerant I/O pads.
3. Ordering information
Table 1.
Ordering information
Package
Name
LPC2292FBD144/01
LPC2292FET144/00
LPC2292FET144/01
LPC2292FET144/G
LQFP144
TFBGA144
TFBGA144
TFBGA144
Description
plastic low profile quad flat package;
144 leads; body 20
20
1.4 mm
plastic thin fine-pitch ball grid array package;
144 balls; body 12
12
0.8 mm
plastic thin fine-pitch ball grid array package;
144 balls; body 12
12
0.8 mm
plastic thin fine-pitch ball grid array package;
144 balls; body 12
12
0.8 mm
Version
SOT486-1
SOT569-2
SOT569-2
SOT569-2
Type number
LPC2292_2294
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 8 June 2011
2 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
Ordering information
…continued
Package
Name
Description
plastic low profile quad flat package;
144 leads; body 20
20
1.4 mm
plastic low profile quad flat package;
144 leads; body 20
20
1.4 mm
plastic low profile quad flat package;
144 leads; body 20
20
1.4 mm
Version
SOT486-1
SOT486-1
SOT486-1
LQFP144
LQFP144
LQFP144
Table 1.
Type number
LPC2294HBD144
LPC2294HBD144/00
LPC2294HBD144/01
3.1 Ordering options
Table 2.
Ordering options
Flash
memory
RAM
CAN
Fast GPIO/
SSP/
Enhanced
UART, ADC,
Timer
yes
no
yes
no
no
no
yes
Temperature range
Type number
LPC2292FBD144/01 256 kB
LPC2292FET144/00
LPC2292FET144/01
LPC2292FET144/G
LPC2294HBD144
256 kB
256 kB
256 kB
256 kB
16 kB
16 kB
16 kB
16 kB
16 kB
16 kB
16 kB
2 channels
2 channels
2 channels
2 channels
4 channels
4 channels
4 channels
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
LPC2294HBD144/00 256 kB
LPC2294HBD144/01 256 kB
LPC2292_2294
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 8 June 2011
3 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
4. Block diagram
TMS
(1)
TDI
(1)
TRST
(1)
TCK
(1)
TDO
(1)
XTAL2
XTAL1 RESET
EMULATION
TRACE MODULE
LPC2292
LPC2294
HIGH-SPEED
GPIO
(4)
48 PINS TOTAL
TEST/DEBUG
INTERFACE
PLL
system
clock
SYSTEM
FUNCTIONS
VECTORED
INTERRUPT
CONTROLLER
ARM7TDMI-S
AHB BRIDGE
P0, P1
ARM7 local bus
INTERNAL
SRAM
CONTROLLER
INTERNAL
FLASH
CONTROLLER
AMBA AHB
(Advanced High-performance Bus)
AHB
DECODER
AHB TO APB
BRIDGE
APB
DIVIDER
CS3 to CS0
(2)
A23 to A0
(2)
BLS3 to BLS0
(2)
OE, WE
(2)
D31 to D0
(2)
SCL
SDA
SCK1
SPI1/SSP
(4)
SERIAL INTERFACE
MOSI1
MISO1
SSEL1
16 kB
SRAM
256 kB
FLASH
EXTERNAL MEMORY
CONTROLLER
EINT3 to EINT0
EXTERNAL
INTERRUPTS
APB (advanced
peripheral bus)
I
2
C-BUS SERIAL
INTERFACE
4
×
CAP0
4
×
CAP1
4
×
MAT0
4
×
MAT1
CAPTURE/
COMPARE
TIMER 0/TIMER 1
AIN3 to AIN0
A/D CONVERTER
AIN7 to AIN4
P0[30:0]
P1[31:16], P1[1:0]
P2[31:0]
P3[31:0]
PWM6 to PWM1
PWM0
CAN
REAL-TIME CLOCK
GENERAL
PURPOSE I/O
UART0/UART1
SPI0
SERIAL INTERFACE
SCK0
MOSI0
MISO0
SSEL0
TXD0, TXD1
RXD0, RXD1
DSR1, CTS1,
DCD1, RI1
TD2, TD1
RD2, RD1
TD4, TD3
(3)
RD4, RD3
(3)
SYSTEM CONTROL
WATCHDOG
TIMER
002aad184
(1) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(2) Pins shared with GPIO.
(3) Available in LPC2294 only.
(4) SSP interface and high-speed GPIO are available on LPC2292/2294/01 only.
Fig 1. Block diagram
LPC2292_2294
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 8 June 2011
4 of 54
NXP Semiconductors
LPC2292/2294
16/32-bit ARM microcontrollers with external memory interface
5. Pinning information
5.1 Pinning
144
109
108
73
37
72
002aad185
1
LPC2292FBD
LPC2294HBD
(1)
36
(1) Pin configuration is identical for devices with and without /00 and /01 suffixes.
Fig 2. LQFP144 pinning
ball A1
index area
LPC2292FET144
(1)
1 2 3 4 5 6 7 8 9 10 11 12 13
A
B
C
D
E
F
G
H
J
K
L
M
N
002aad191
Transparent top view
(1) Pin configuration is identical for devices with and without /00 and /01 suffixes.
Fig 3. TFBGA144 pinning
LPC2292_2294
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 8 June 2011
5 of 54
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