HIGH-SPEED
16K x 8 DUAL-PORT
STATIC RAM
Features
◆
◆
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IDT7006S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7006S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7006L
Active: 700mW (typ.)
Standby: 1mW (typ.)
IDT7006 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for
BUSY
output flag on Master,
M/S = L for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001V
electrostatic discharge
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin
TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
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Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
A
13L
A
0L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
(1,2)
Address
Decoder
14
MEMORY
ARRAY
14
Address
Decoder
A
13R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
M/S
SEM
R
(2)
INT
R
2739 drw 01
JULY 2018
1
DSC- 2739/18
©2018 Integrated Device Technology, Inc.
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7006 is a high-speed 16K x 8 Dual-Port Static RAM. The
IDT7006 is designed to be used as a stand-alone 128K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE
permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power. Low-power (L)
versions offer battery backup data retention capability with typical power
consumption of 500µW from a 2V battery.
The IDT7006 is packaged in a ceramic 68-pin PGA, an 68-pin quad
flatpack, a PLCC, and a 64-pin thin quad flatpack, TQFP. Military grade
product is manufactured in compliance with the latest revision of MIL-PRF-
38535 QML, Class B, making it ideally suited to military temperature
applications demanding the highest level of performance and reliability.
Pin Configurations
(1,2,3)
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O
1L
I/O
0L
N/C
OE
L
R/W
L
SEM
L
CE
L
N/C
A
13L
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
11/06/01
IDT7006J or F
J68
(4)
F68
(4)
68 Pin PLCC / Flatpack
Top View
(5)
55
54
53
52
51
50
49
48
47
46
45
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
2739 drw 02a
.
I/O
1L
I/O
0L
R/W
L
SEM
L
CE
L
A
13L
V
CC
A
12L
A
11L
I/O
7R
N/C
OE
R
R/W
R
SEM
R
CE
R
N/C
A
13R
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
OE
L
A
10L
A
9L
A
8L
A
7L
A
6L
A
5L
49
11/06/01
INDEX
61
60
63
62
64
58
57
59
56
55
54
53
52
51
50
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in. x .17 in.
F68-1 package body is approximately .97 in x .97 in x .08 in.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
.
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
7006PF
PN64
(4)
64 Pin TQFP
Top View
(5)
SEM
R
CE
R
I/O
7R
OE
R
R/W
R
A
9R
A
8R
A
7R
A
13R
GND
I/O
6R
A
12R
A
11R
A
10R
A
6R
A
5R
2739 drw 03a
2
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
(con't.)
51
11
53
A
7L
55
A
9L
A
5L
52
A
6L
54
A
8L
50
A
4L
49
A
3L
48
A
2L
47
A
1L
46
44
42
A
0L
BUSY
L
M/S
40
38
INT
R
A
1R
36
A
3R
35
A
4R
32
A
7R
30
A
9R
11/06/01
10
45
43
41
39
37
INT
L
GND
BUSY
R
A
0R
A
2R
34
A
5R
33
A
6R
31
A
8R
09
08
57
56
A
11L
A
10L
59
58
V
CC
A
12L
61
60
N/C A
13L
63
62
SEM
L
CE
L
65
64
OE
L
R/W
L
67
66
I/O
0L
N/C
1
3
68
I/O
1L
I/O
2L
I/O
4L
2
4
I/O
5L
I/O
3L
B
C
5
7
9
11
13
15
GND I/O
7L
GND I/O
1R
V
CC
I/O
4R
6
I/O
6L
D
8
10
12
14
16
V
CC
I/O
0R
I/O
2R
I/O
3R
I/O
5R
E
F
G
H
J
07
IDT7006G
G68
(4)
68-Pin PGA
Top View
(5)
28
29
A
11R
A
10R
26
27
GND A
12R
24
N/C
25
A
13R
06
05
04
22
23
SEM
R
CE
R
20
OE
R
21
R/W
R
.
03
02
18
19
I/O
7R
N/C
17
I/O
6R
K
L
2739 drw 04a
01
A
INDEX
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking
Pin Names
Left Port
CE
L
R/W
L
OE
L
A
0L
- A
13L
I/O
0L
- I/O
7L
SEM
L
INT
L
BUSY
L
CE
R
R/W
R
OE
R
A
0R
- A
13R
I/O
0R
- I/O
7R
SEM
R
INT
R
BUSY
R
M/S
V
CC
GND
Right Port
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2739 tbl 01
Names
6.42
3
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs
(1)
Outputs
CE
H
L
L
X
R/W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
I/O
0-7
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power-Down
Write to Memory
Read Memory
Outputs Disabled
Mode
NOTE:
1. A
0L
– A
13L
is not equal to A
0R
– A
13R
2739 tbl 02
Truth Table II: Semaphore Read/Write Control
(1)
Inputs
(1)
Outputs
CE
H
H
L
R/W
H
↑
X
OE
L
X
X
SEM
L
L
L
I/O
0-7
DATA
OUT
DATA
IN
____
Mode
Read in Semaphore Flag Data Out
Write I/Oo into Semaphore Flag
Not Allowed
2739 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from I/O
0 -
I/O
7
. These eight semaphores are addressed by A
0
- A
2
.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Military
-0.5 to +7.0
Unit
V
Recommended DC Operating
Conditions
Symbol
V
CC
GND
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
2739 tbl 06
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
o
C
C
V
IH
V
IL
o
mA
NOTES:
1. V
IL
> -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
2739 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sec-tions of this specification is not implied. Exposure
to absolute maxi-mum rating conditions for extended periods may affect
reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
< Vcc + 10%.
Maximum Operating Temperature
and Supply Voltage
(1)
Grade
Military
Commercial
Ambient
Temperature
-55
O
C to+125
O
C
0
O
C to +70
O
C
40
O
C to +85
O
C
GND
0V
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
5.0V
+
10%
Capacitance
(1)
(T
A
= +25°C, f = 1.0mhz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output
Capacitance
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
Industrial
2739 tbl 07
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
2739 tbl 05
NOTES:
1. These parameters are determined by device characterization, but are not
production tested (TQFP Package Only).
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
4
IDT7006S/L
High-Speed 16K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the 0perating
Temperature and Supply Voltage Range
(V
CC
= 5.0V ± 10%)
7006S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OH
= -4mA
Min.
___
___
___
7006L
Max.
10
10
0.4
___
Min.
___
___
___
Max.
5
5
0.4
___
Unit
µA
µA
V
V
2739 tbl 08
2.4
2.4
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
Data Retention Characteristics Over All Temperature Ranges
(L Version Only)
(V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
Symbol
V
DR
I
CCDR
Parameter
V
CC
for Data Retention
Data Retention Current
V
CC
= 2
V
CE
> V
HC
V
IN
> V
HC
or < V
LC
t
CDR
(3)
t
R
(3)
Chip Deselect to Data Retention Time
Operation Recovery Time
SEM
> V
HC
Mil. & Ind.
Com'l.
Test Condition
Min.
2.0
___
Typ.
___
(1)
Max.
___
Unit
V
µA
100
100
___
___
4000
1500
___
___
___
0
t
RC
(2)
ns
ns
2739 tbl 09
NOTES:
1. T
A
= +25°C, V
CC
= 2V, and are not production tested.
2. t
RC
= Read Cycle Time
3. This parameter is guaranteed by characterization, but is not production tested.
Data Retention Waveform
DATA RETENTION MODE
V
CC
4.5V
t
CDR
CE
V
IH
V
DR
V
DR
>
2V
4.5V
t
R
V
IH
2739 drw 05
6.42
5
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