SiT9002
LVPECL / HCSL / LVDS / CML
1 to 220 MHz High Performance Spread Spectrum Oscillator
Features
• World’s first differential spread spectrum oscillator
• Extremely low cycle-cycle jitter
• As low as10 ps (typical)
• Wide frequency range
• 1 MHz to 220 MHz
• 220 MHz to 800 MHz (contact SiTime)
• Eight spread selections (31.5 KHz modulation rate)
• Center Spread: ±0.25%, ±0.5%, ±1.0%, ±2.0%
• Down Spread: -0.5%, -1.0%, -2.0%, -4.0%
• For -0.25% and ±0.125% contact SiTime
• Low frequency stability (Spread = OFF)
• ±25 ppm or ±50 ppm
• Operating voltage
• 1.8V or 2.5 or 3.3 V
• Operating temperature range:
• Industrial, -40°C to 85°C
• Extended Commercial, -20°C to 70°C
• Small footprint
• 5.0 x 3.2 x 0.75 mm
• 7.0 x 5.0 x 0.90 mm
• Pb-free and RoHS compliant
• Ultra-reliable start up and greater immunity from inter-
ference
Benefits
• Services most PC peripherals, networking, and consumer
applications
• Provides wide range of spread percentage for maximum
electromagnetic interference (EMI) reduction
• Up to -17 dB reduction on third homonic and -12dB on the
fundamental
• Fast time to market due to not needing to redesign the PCB
for EMI reduction
• Factory programmable for ultra-fast lead time
• No crystal or load capacitors required
• Eliminates crystal qualification time
• 50%+ board saving space
• Completely quartz-free
Applications
• PCI-Express
• USB 3.0
• Fully Buffered DIMM
• Blade Server
• Router
• System Clock
• Networking and Computing
• Automotive
• Industrial
Block Diagram
Pinout
SiTime Corporation
Rev. 1.11
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised September 27, 2016
SiT9002
LVPECL / HCSL / LVDS / CML
1 to 220 MHz High Performance Spread Spectrum Oscillator
Pin Description
Pin No.
1
Name
ST/OE/SD
Input
Pin Description
Standby or Output Enable pin for OUT+ and OUT-.
OE:
When High or Open : OUT+ and OUT- = active
When Low : OUT+ and OUT- = High Impedance state
ST:
When High or Open : OUT+ and OUT- = active
When Low : OUT+ and OUT- = Output is low (weak pull down), oscillation stops
SD: Spread Disable - disables spread spectrum
When High or Open : Spread Spectrum modulation = active
When Low : Spread Spectrum modulation = Off
No connect pin, leave it floating.
VDD power supply ground. Connect to ground
1 to 220 MHz programmable clock output. For frequencies > 220 MHz contact SiTime
Power supply
2
3
4
5
6
NC
GND
OUT+
OUT-
VDD
NA
Power
Output
Output
Power
Absolute Maximum Ratings
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual
performance of the IC is only guaranteed within the operational specifications, not absolute maximum ratings.
Ab
solute Maximum Table
Parameter
Storage Temperature
VDD
Vin
Theta JA ( with copper plane on VDD and GND) 5.0 x 3.2 package
7.0 x 5.0 package when center pad is soldered down
7.0 x 5.0 package when center pad is not soldered down
Theta JC (with PCB traces of 0.010 inch to all pins) 5.0 x 3.2 package
7.0 x 5.0 package when center pad is soldered down
7.0 x 5.0 package when center pad is not soldered down
Soldering Temperature (follow standard Pb free soldering guidelines)
Number of Program Writes
Program Retention over -40 to 125C, Process, VDD (0 to 3.6V)
Human Body Model (JESD22-A114)
Charged Device Model (JESD22-C101)
Machine Model (JESD22-A115)
Min.
-65
-0.5
GND - 0.5
–
–
–
–
–
–
–
–
–
2000
750
200
Max.
150
4
VDD + 0.5
68
38
90
45
35
48
260
1
1,000+
–
–
–
Unit
°C
V
V
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
NA
years
V
–
–
DC Electrical Specifications
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
MIL-STD-883F, Method 1010-65-150°C (1000 cycle)
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.11
Page 2 of 12
www.sitime.com
SiT9002
LVPECL / HCSL / LVDS / CML
1 to 220 MHz High Performance Spread Spectrum Oscillator
LVCMOS input, OE or ST pin, 3.3V ± 10% or 2.5V ± 10% or 1.8V ± 5%, -40 to 85°C
Symbol
V
IH
V
IL
I
IH
I
IL
T
pu
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Power Up Time
OE or ST or SD pin
OE or ST or SD pin
Time from minimum power supply voltage to the
first cycle (Guaranteed no runt pulses)
Condition
Min.
70
–
–
-10
–
Typ.
–
–
–
–
–
Max.
–
30
10
–
10
Unit
%Vdd
%Vdd
uA
uA
ms
LVPECL, 3.3V ± 10% or 2.5V ± 10%, -40 to 85°C
Symbol
V
DD
I
DD
V
OH
V
OL
V
swing
Parameter
Supply Voltage
Supply Current
Output High Voltage
Output Low Voltage
Pk-Pk Output Voltage Swing
V
DD
= 3.3, Excluding Load Termination Current
V
DD
= 2.5, Excluding Load Termination Current
50 Ohm termination to V
DD
- 2.0V
See Figure 2,3.
Condition
Min.
2.97
2.25
–
–
V
DD
-1.1
V
DD
-2.0
600
Typ.
3.3
2.5
75
75
–
–
800
Max.
3.63
2.75
84
84
V
DD
-0.7
V
DD
-1.4
1000
Unit
V
V
mA
mA
V
V
mV
HCSL, 3.3V ±10% or 2.5V ±10%, -40 to 85°C
Symbol
V
DD
I
DD
V
OH
V
OL
V
swing
Parameter
Supply Voltage
Supply Current
Output High Voltage
Output Low Voltage
Pk-Pk Output Voltage Swing
V
DD
= 3.3, Excluding Load Termination Current
V
DD
= 2.5, Excluding Load Termination Current
50 Ohm termination to GND
See Figure 4.
Condition
Min.
2.97
2.25
–
–
0.6
0.0
600
Typ.
3.3
2.5
73
73
0.75
–
750
Max.
3.63
2.75
80
80
0.95
50
950
Unit
V
V
mA
mA
V
mV
mV
LVDS, 3.3V ± 10% or 2.5V ± 10%, -40 to 85°C
Symbol
V
DD
I
DD
V
OD1
∆
V
OD1
V
OS1
∆
V
OS1
V
OD2
∆
V
OD2
V
OS2
∆
V
OS2
V
OD3
∆
V
OD3
V
OS3
∆
V
OS3
Parameter
Supply Voltage
Supply Current
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Swing Mode = High
Double load termination.
See Figure 6.
Swing Mode = High
Single load termination.
See Figure 5.
V
DD
= 3.3, Excluding Load Termination Current
V
DD
= 2.5, Excluding Load Termination Current
Swing Mode = Normal
Single load termination.
See Figure 5.
Condition
Min.
2.97
2.25
–
–
250
–
–
–
500
–
–
–
250
–
–
–
Typ.
3.3
2.5
75
70
350
–
1.2
–
700
–
1.2
–
350
–
1.2
–
Max.
3.63
2.75
85
77
450
50
–
50
900
50
–
50
450
50
–
50
Unit
V
V
mA
mA
mV
mV
V
mV
mV
mV
V
mV
mV
mV
V
mV
Rev. 1.11
Page 3 of 12
www.sitime.com
SiT9002
LVPECL / HCSL / LVDS / CML
1 to 220 MHz High Performance Spread Spectrum Oscillator
CML, 3.3V ± 10% or 2.5V ± 10% or 1.8V ± 5%, -40 to 85°C
Symbol
V
DD
Parameter
Supply Voltage
Condition
Min.
2.97
2.25
1.71
I
DD
Supply Current
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= 1.8V
V
OH1
V
OL1
V
swing1
V
OH2
V
OL2
V
swing2
V
OH3
V
OL3
V
swing3
Output High Voltage
Output Low Voltage
Pk-Pk Output Voltage Swing
Output High Voltage
Output Low Voltage
Pk-Pk Output Voltage Swing
Output High Voltage
Output Low Voltage
Pk-Pk Output Voltage Swing
Swing Mode = Normal
Single Load Termination
See Figure 7.
Swing Mode = High
Single Load Termination
See Figure 7.
Swing Mode = High
Double Load Termination
See Figure 8.
Excluding Load
Termination
Current
–
–
–
V
DD
-0.1
300
V
DD
-0.1
V
DD
-1.1
Typ.
3.3
2.5
1.8
48
48
48
–
425
–
V
DD
-0.85
Max.
3.63
2.75
1.89
51
51
51
V
DD
V
DD
-0.3
Unit
V
V
V
mA
mA
mA
V
V
mV
V
V
mV
V
V
mV
V
DD
-0.55 V
DD
-0.425
550
V
DD
V
DD
-0.6
600
V
DD
-0.1
300
850
–
425
1100
V
DD
V
DD
-0.3
V
DD
-0.55 V
DD
-0.425
550
AC Electrical Specifications
LVPECL, 3.3V ± 10%, -40 to 85°C
Symbol
F
out
F
stab
Parameter
Output Frequency
Frequency Stability
Inclusive of initial stability,
operating temp., rated power
supply voltage change, load
change
First year @ 25°C
20% to 80%
F
out
= 100 MHz, -0.5% down spread
F
out
= 150 MHz, -0.5% down spread
F
out
= 200 MHz, -0.5% down spread
-20 to 70°C
-40 to 85°C
Condition
Min.
1.0
-25
-50
–
45
100
–
–
–
Typ.
–
–
–
–
–
150
10
8
8
Max.
220
+25
+50
1
55
300
16
14
14
Unit
MHz
ppm
ppm
PPM
%
ps
ps
ps
ps
F
age
DC
t
R
/t
F
T
CCJ
Aging
Duty Cycle
Output Rise/Fall Time
Cycle-Cycle Jitter
LVPECL, 2.5V ± 10%, -40 to 85°C
Symbol
F
out
F
stab
Parameter
Output Frequency
Frequency Stability
Inclusive of initial stability,
operating temp., rated power
supply voltage change, load
change
First year @ 25°C
20% to 80%
F
out
= 100 MHz, -0.5% down spread
F
out
= 150 MHz, -0.5% down spread
F
out
= 200 MHz, -0.5% down spread
-20 to 70°C
-40 to 85°C
Condition
Min.
1.0
-25
-50
–
45
100
–
–
–
Typ.
–
–
–
–
–
150
10
8
8
Max.
220
+25
+50
1
55
300
16
14
14
Unit
MHz
ppm
ppm
PPM
%
ps
ps
ps
ps
F
age
DC
t
R
/t
F
T
CCJ
Aging
Duty Cycle
Output Rise/Fall Time
Cycle-Cycle Jitter
Rev. 1.11
Page 4 of 12
www.sitime.com
SiT9002
LVPECL / HCSL / LVDS / CML
1 to 220 MHz High Performance Spread Spectrum Oscillator
HCSL, 3.3V ± 10%, -40 to 85°C
Symbol
F
out
F
stab
Parameter
Output Frequency
Frequency Stability
Inclusive of initial stability,
operating temp., rated power
supply voltage change, load
change
First year @ 25°C
20% to 80%
F
out
= 100 MHz, -0.5% down spread
F
out
= 150 MHz, -0.5% down spread
F
out
= 200 MHz, -0.5% down spread
-20 to 70°C
-40 to 85°C
Condition
Min.
1.0
-25
-50
–
45
200
–
–
–
Typ.
–
–
–
–
–
280
10
10
10
Max.
220
+25
+50
1
55
375
16
15
15
Unit
MHz
ppm
ppm
PPM
%
ps
ps
ps
ps
F
age
DC
t
R
/t
F
T
CCJ
Aging
Duty Cycle
Output Rise/Fall Time
Cycle-Cycle Jitter
HCSL, 2.5V ± 10%, -40 to 85°C
Symbol
F
out
F
stab
Parameter
Output Frequency
Frequency Stability
Inclusive of initial stability,
operating temp., rated power
supply voltage change, load
change
First year @ 25°C
20% to 80%
F
out
= 100 MHz, -0.5% down spread
F
out
= 150 MHz, -0.5% down spread
F
out
= 200 MHz, -0.5% down spread
-20 to 70°C
-40 to 85°C
Condition
Min.
1.0
-25
-50
–
45
200
–
–
–
Typ.
–
–
–
–
–
300
9
9
9
Max.
220
+25
+50
1
55
400
19
17
15
Unit
MHz
ppm
ppm
PPM
%
ps
ps
ps
ps
F
age
DC
t
R
/t
F
T
CCJ
Aging
Duty Cycle
Output Rise/Fall Time
Cycle-Cycle Jitter
LVDS, 3.3V ± 10%, -40 to 85°C
Symbol
F
out
F
stab
Parameter
Output Frequency
Frequency Stability
Inclusive of initial stability,
operating temp., rated power
supply voltage change, load
change
First year @ 25°C
20% to 80%
F
out
= 100 MHz, -0.5% down spread
F
out
= 150 MHz, -0.5% down spread
F
out
= 200 MHz, -0.5% down spread
-20 to 70°C
-40 to 85°C
Condition
Min.
1.0
-25
-50
–
45
100
–
–
–
Typ.
–
–
–
–
–
200
11
11
11
Max.
220
+25
+50
1
55
325
19
20
21
Unit
MHz
ppm
ppm
PPM
%
ps
ps
ps
ps
F
age
DC
t
R
/t
F
T
CCJ
Aging
Duty Cycle
Output Rise/Fall Time
Cycle-Cycle Jitter
Rev. 1.11
Page 5 of 12
www.sitime.com
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
