1 Megabit (128K x 8) Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Data Sheet
FEATURES:
• Single Voltage Read and Write Operations
– 5.0V-only for the 29EE010
– 3.0V-only for the 29LE010
– 2.7V-only for the 29VE010
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
• Fast Page-Write Operation
– 128 Bytes per Page, 1024 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 5 sec (typical)
– Effective Byte-write Cycle Time: 39 µs
(typical)
• Fast Read Access Time
– 5.0V-only operation: 90 and 120 ns
– 3.0V-only operation: 150 and 200 ns
– 2.7V-only operation: 200 and 250 ns
• Latched Address and Data
• Automatic Write Timing
– Internal V
pp
Generation
• End of Write Detection
– Toggle Bit
– Data# Polling
• Hardware and Software Data Protection
• TTL I/O Compatibility
• JEDEC Standard Byte-wide EEPROM Pinouts
• Packages Available
– 32-Pin TSOP (8x20 & 8x14 mm)
– 32-Lead PLCC
– 32 Pin Plastic DIP
1
2
3
4
5
6
7
PRODUCT DESCRIPTION
The 29EE010/29LE010/29VE010 are 128K x 8 CMOS
page mode EEPROMs manufactured with SST’s propri-
etary, high performance CMOS SuperFlash technology.
The split gate cell design and thick oxide tunneling
injector attain better reliability and manufacturability
compared with alternate approaches. The 29EE010/
29LE010/29VE010 write with a single power supply.
Internal Erase/Program is transparent to the user. The
29EE010/29LE010/29VE010 conform to JEDEC stan-
dard pinouts for byte-wide memories.
Featuring high performance page write, the 29EE010/
29LE010/29VE010 provide a typical byte-write time of
39 µsec. The entire memory, i.e., 128K bytes, can be
written page by page in as little as 5 seconds, when using
interface features such as Toggle Bit or Data# Polling to
indicate the completion of a write cycle. To protect
against inadvertent write, the 29EE010/29LE010/
29VE010 have on-chip hardware and software data
protection schemes. Designed, manufactured, and
tested for a wide spectrum of applications, the 29EE010/
29LE010/29VE010 are offered with a guaranteed page-
write endurance of 10
4
or 10
3
cycles. Data retention is
rated at greater than 100 years.
The 29EE010/29LE010/29VE010 are suited for applica-
tions that require convenient and economical updating of
program, configuration, or data memory. For all system
applications, the 29EE010/29LE010/29VE010 signifi-
cantly improve performance and reliability, while lower-
ing power consumption, when compared with floppy disk
or EPROM approaches. The 29EE010/29LE010/
29VE010 improve flexibility while lowering the cost for
program, data, and configuration storage applications.
To meet high density, surface mount requirements, the
29EE010/29LE010/29VE010 are offered in 32-pin
TSOP and 32-lead PLCC packages. A 600-mil, 32-pin
PDIP package is also available. See Figures 1 and 2 for
pinouts.
Device Operation
The SST page mode EEPROM offers in-circuit electrical
write capability. The 29EE010/29LE010/29VE010 does
not require separate erase and program operations. The
internally timed write cycle executes both erase and
program transparently to the user. The 29EE010/
29LE010/29VE010 have industry standard optional
Software Data Protection, which SST recommends al-
ways to be enabled. The 29EE010/29LE010/29VE010
are compatible with industry standard EEPROM pinouts
and functionality.
Read
The Read operations of the 29EE010/29LE010/
29VE010 are controlled by CE# and OE#, both have to
be low for the system to obtain data from the outputs.
CE# is used for device selection. When CE# is high, the
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16
© 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice.
304-04 12/97
1
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
chip is deselected and only standby power is consumed.
OE# is the output control and is used to gate data from
the output pins. The data bus is in high impedance state
when either CE# or OE# is high. Refer to the read cycle
timing diagram for further details (Figure 3).
Write
The Page Write to the SST29EE010/29LE010/29VE010
should always use the JEDEC Standard Software Data
Protection (SDP) 3-byte command sequence. The
29EE010/29LE010/29VE010 contain the optional
JEDEC approved Software Data Protection scheme.
SST recommends that SDP always be enabled, thus, the
description of the Write operations will be given using the
SDP enabled format.
The 3-byte SDP Enable and SDP
Write commands are identical; therefore, any time a
SDP Write command is issued, software data protec-
tion is automatically assured.
The first time the 3-byte
SDP command is given, the device becomes SDP en-
abled. Subsequent issuance of the same command
bypasses the data protection for the page being written.
At the end of the desired page write, the entire device
remains protected. For additional descriptions, please
see the application notes on “The Proper Use of JEDEC
Standard Software Data Protection” and “Protecting
Against Unintentional Writes When Using Single Power
Supply Flash Memories” in this data book.
The Write operation consists of three steps. Step 1 is the
three byte load sequence for Software Data Protection.
Step 2 is the byte-load cycle to a page buffer of the
29EE010/29LE010/29VE010. Steps 1 and 2 use the
same timing for both operations. Step 3 is an internally
controlled write cycle for writing the data loaded in the
page buffer into the memory array for nonvolatile stor-
age. During both the SDP 3-byte load sequence and the
byte-load cycle, the addresses are latched by the falling
edge of either CE# or WE#, whichever occurs last. The
data is latched by the rising edge of either CE# or WE#,
whichever occurs first. The internal write cycle is initiated
by the T
BLCO
timer after the rising edge of WE# or CE#,
whichever occurs first. The write cycle, once initiated, will
continue to completion, typically within 5 ms. See Fig-
ures 4 and 5 for WE# and CE# controlled page write cycle
timing diagrams and Figures 14 and 16 for flowcharts.
The Write operation has three functional cycles: the
Software Data Protection load sequence, the page load
cycle, and the internal write cycle. The Software Data
Protection consists of a specific three byte load se-
quence that allows writing to the selected page and will
leave the 29EE010/29LE010/29VE010 protected at the
end of the page write. The page load cycle consists of
loading 1 to 128 bytes of data into the page buffer. The
internal write cycle consists of the T
BLCO
time-out and the
write timer operation. During the Write operation, the only
valid reads are Data# Polling and Toggle Bit.
The Page-Write operation allows the loading of up to 128
bytes of data into the page buffer of the 29EE010/
29LE010/29VE010 before the initiation of the internal
write cycle. During the internal write cycle, all the data in
the page buffer is written simultaneously into the memory
array. Hence, the page-write feature of 29EE010/
29LE010/29VE010 allow the entire memory to be written
in as little as 5 seconds. During the internal write cycle,
the host is free to perform additional tasks, such as to
fetch data from other locations in the system to set up the
write to the next page. In each Page-Write operation, all
the bytes that are loaded into the page buffer must have
the same page address, i.e. A
7
through A
16
. Any byte not
loaded with user data will be written to FF.
See Figures 4 and 5 for the page-write cycle timing
diagrams. If after the completion of the 3-byte SDP load
sequence or the initial byte-load cycle, the host loads a
second byte into the page buffer within a byte-load cycle
time (T
BLC
) of 100 µs, the 29EE010/29LE010/29VE010
will stay in the page load cycle. Additional bytes are then
loaded consecutively. The page load cycle will be termi-
nated if no additional byte is loaded into the page buffer
within 200 µs (T
BLCO
) from the last byte-load cycle, i.e.,
no subsequent WE# or CE# high-to-low transition after
the last rising edge of WE# or CE#. Data in the page
buffer can be changed by a subsequent byte-load cycle.
The page load period can continue indefinitely, as long
as the host continues to load the device within the byte-
load cycle time of 100 µs. The page to be loaded is
determined by the page address of the last byte loaded.
Software Chip-Erase
The 29EE010/29LE010/29VE010 provide a Chip-Erase
operation, which allows the user to simultaneously clear
the entire memory array to the “1” state. This is useful
when the entire device must be quickly erased.
The Software Chip-Erase operation is initiated by using
a specific six byte-load sequence. After the load se-
quence, the device enters into an internally timed cycle
similar to the write cycle. During the erase operation, the
only valid read is Toggle Bit. See Table 4 for the load
sequence, Figure 9 for timing diagram, and Figure 18 for
the flowchart.
© 1998 Silicon Storage Technology, Inc.
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304-04 12/97
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Write Operation Status Detection
The 29EE010/29LE010/29VE010 provide two software
means to detect the completion of a write cycle, in order
to optimize the system write cycle time. The software
detection includes two status bits: Data# Polling (DQ
7
)
and Toggle Bit (DQ
6
). The end of write detection mode is
enabled after the rising WE# or CE# whichever occurs
first, which initiates the internal write cycle.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ
7
or DQ
6
. In order to
prevent spurious rejection, if an erroneous result occurs,
the software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the write
cycle, otherwise the rejection is valid.
Data# Polling (DQ
7
)
When the 29EE010/29LE010/29VE010 are in the inter-
nal write cycle, any attempt to read DQ
7
of the last byte
loaded during the byte-load cycle will receive the com-
plement of the true data. Once the write cycle is com-
pleted, DQ
7
will show true data. The device is then ready
for the next operation. See Figure 6 for Data# Polling
timing diagram and Figure 15 for a flowchart.
Toggle Bit (DQ
6
)
During the internal write cycle, any consecutive attempts
to read DQ
6
will produce alternating 0’s and 1’s, i.e.
toggling between 0 and 1. When the write cycle is
completed, the toggling will stop. The device is then
ready for the next operation. See Figure 7 for Toggle Bit
timing diagram and Figure 15 for a flowchart. The initial
read of the Toggle Bit will typically be a “1”.
Data Protection
The 29EE010/29LE010/29VE010 provide both hard-
ware and software features to protect nonvolatile data
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.
V
CC
Power Up/Down Detection: The write operation is
inhibited when V
CC
is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the write operation. This prevents inad-
vertent writes during power-up or power-down.
Software Data Protection (SDP)
The 29EE010/29LE010/29VE010 provide the JEDEC
approved optional software data protection scheme for
all data alteration operations, i.e., Write and Chip erase.
With this scheme, any write operation requires the inclu-
sion of a series of three byte-load operations to precede
the data loading operation. The three byte-load se-
quence is used to initiate the write cycle, providing
optimal protection from inadvertent write operations,
e.g., during the system power-up or power-down. The
29EE010/29LE010/29VE010 are shipped with the soft-
ware data protection disabled.
The software protection scheme can be enabled by
applying a three-byte sequence to the device, during a
page-load cycle (Figures 4 and 5). The device will then
be automatically set into the data protect mode. Any
subsequent write operation will require the preceding
three-byte sequence. See Table 4 for the specific soft-
ware command codes and Figures 4 and 5 for the timing
diagrams. To set the device into the unprotected mode,
a six-byte sequence is required. See Table 4 for the
specific codes and Figure 8 for the timing diagram. If a
write is attempted while SDP is enabled the device will be
in a non-accessible state for ~ 300 µs. SST recommends
Software Data Protection always be enabled. See Figure
16 for flowcharts.
The 29EE010/29LE010/29VE010 Software Data Pro-
tection is a global command, protecting (or unprotecting)
all pages in the entire memory array once enabled (or
disabled). Therefore using SDP for a single page write
will enable SDP for the entire array. Single pages by
themselves cannot be SDP enabled or disabled.
1
2
3
4
5
6
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10
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© 1998 Silicon Storage Technology, Inc.
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304-04 12/97
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
Single power supply reprogrammable nonvolatile
memories may be unintentionally altered. SST strongly
recommends that Software Data Protection (SDP) al-
ways be enabled. The 29EE010/29LE010/29VE010
should be programmed using the SDP command se-
quence. SST recommends the SDP Disable Command
Sequence not be issued to the device prior to writing.
Please refer to the following Application Notes located at
the back of this databook for more information on using
SDP:
•
•
Protecting Against Unintentional Writes When Using
Single Power Supply Flash Memories
The Proper Use of JEDEC Standard Software Data
Protection
Product Identification Mode Exit
In order to return to the standard read mode, the Soft-
ware Product Identification mode must be exited. Exiting
is accomplished by issuing the Software ID Exit (reset)
operation, which returns the device to the read operation.
The Reset operation may also be used to reset the
device to the read mode after an inadvertent transient
condition that apparently causes the device to behave
abnormally, e.g. not read correctly. See Table 4 for
software command codes, Figure 11 for timing wave-
form and Figure 17 for a flowchart.
multiple manufacturers in the same socket. For details,
see Table 3 for hardware operation or Table 4 for
software operation, Figure 10 for the software ID entry
and read timing diagram and Figure 17 for the ID entry
command sequence flowchart. The manufacturer and
device codes are the same for both operations.
T
ABLE
1: P
RODUCT
I
DENTIFICATION
T
ABLE
Manufacturer’s Code
29EE010 Device Code
29LE010 Device Code
29VE010 Device Code
Byte
0000 H
0001 H
0001 H
0001 H
Data
BF H
07 H
08 H
08 H
304 PGM T1.1
Product Identification
The product identification mode identifies the device as
the 29EE010/29LE010/29VE010 and manufacturer as
SST. This mode may be accessed by hardware or
software operations. The hardware operation is typically
used by a programmer to identify the correct algorithm
for the 29EE010/29LE010/29VE010. Users may wish to
use the software product identification operation to iden-
tify the part (i.e. using the device code) when using
F
UNCTIONAL
B
LOCK
D
IAGRAM OF
SST 29EE010/29LE010/29VE010
X-Decoder
1,048,576 Bit
EEPROM
Cell Array
A
16
- A
0
Address buffer & Latches
Y-Decoder and Page Latches
CE#
OE#
WE#
Control Logic
I/O Buffers and Data Latches
DQ
7
- DQ
0
304 MSW B1.0
© 1998 Silicon Storage Technology, Inc.
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304-04 12/97
1 Megabit Page Mode EEPROM
SST29EE010, SST29LE010, SST29VE010
A11
A9
A8
A13
A14
NC
WE#
Vcc
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
Top View
Die up
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
304 MSW F01.1
1
2
3
4
5
F
IGURE
1: P
IN
A
SSIGNMENTS FOR
32-
PIN
TSOP P
ACKAGES
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
23
22
21
20
19
18
17
Vcc
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
DQ1
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
4
A12
A15
A16
NC
WE#
Vcc
NC
6
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
3
2
1
32 31 30
29
28
27
26
7
8
9
304 MSW F02.1
32-Pin PDIP
Top View
24
32-Lead PLCC
Top View
25
24
23
22
21
14 15 16
17 18 19
20
DQ2
Vss
DQ4
DQ6
DQ3
DQ5
10
F
IGURE
2: P
IN
A
SSIGNMENTS FOR
32-
PIN
P
LASTIC
DIP
S AND
32-
LEAD
PLCC
S
T
ABLE
2: P
IN
D
ESCRIPTION
Symbol
Pin Name
A
16
-A
7
Row Address Inputs
A
6
-A
0
DQ
7
-DQ
0
Column Address
Inputs
Data Input/output
11
Functions
To provide memory addresses. Row addresses define a page for a
write cycle.
Column Addresses are toggled to load page data.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are in
tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the write operations
To provide 5-volt supply (± 10%) for the 29EE010, 3-volt supply (3.0-3.6V)
for the 29LE010 and 2.7-volt supply (2.7-3.6V) for the 29VE010
Unconnected pins.
304 PGM T2.0
12
13
14
CE#
OE#
WE#
Vcc
Vss
NC
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
15
16
© 1998 Silicon Storage Technology, Inc.
5
304-04 12/97
stm32/stm8
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