5 Applications Information ............................................................................................................................................. 9
5.1 Important Assembly Guidelines ............................................................................................................................. 9
5.2 PCB Land Pattern and Paste Stencil ..................................................................................................................... 9
7 Ordering Information .................................................................................................................................................. 10
9 Revision History ......................................................................................................................................................... 11
2
DS1072PP1
CS7250B
1 Pin Descriptions
1 Pin Descriptions
1.1 LGA Pinout
3
4
5
2
1
Figure 1-1. Top-Down (Through-Package) View
1.2 Pin Descriptions
A description of each pin on the CS7250B is provided in
Table 1-1.
Table 1-1. Pin Descriptions
Name
DATA
LRSEL
Pin #
1
2
I/O
O
I
PDM data output
Channel select
0 = Data output following falling CLK edge
1 = Data output following rising CLK edge
This pin must be tied to VDD or GND—there is no internal pull-up/-down provided.
Ground
I
Clock input
Power supply
Description
GND
CLK
VDD
3
4
5
3
DS1072PP1
CS7250B
2 Typical Connection Diagram
2 Typical Connection Diagram
1.8V
0.1µF
1.8V
0.1µF
AVDD
VDD
GND
VDD
GND
CS7250B
CS7250B
CLK
AP/CODEC
DATA
LRSEL
CLK
DATA
LRSEL
CLK
DATA
Figure 2-1. Typical Connection Diagram
Stereo connection of two CS7250B digital microphones is shown in
Fig. 2-1.
It is recommended to connect a 0.1-F decoupling capacitor between the VDD and GND pins of the CS7250B. A ceramic
0.1-F capacitor with X7R dielectric or better is suitable. The capacitor should be placed as close to the CS7250B as
possible.
4
DS1072PP1
CS7250B
3 Characteristics and Specifications
3 Characteristics and Specifications
Table 3-1. Parameter Definitions
Definition
Sensitivity
A measure of the microphone output response to the acoustic pressure of a 1-kHz, 94 dB SPL (1 Pa RMS)
sine wave. This is referenced to the output Full Scale Range (FSR) of the microphone.
Full Scale Range (FSR)
Sensitivity, electrical noise floor and power supply rejection are measured with reference to the output full
scale range (FSR) of the microphone. FSR is defined as the amplitude of a 1-kHz sine-wave output whose
positive peak value reaches 100% density of logic 1s and whose negative peak value reaches 0% density
of logic 1s. This is the largest 1-kHz sine wave that fits in the digital output range without clipping. Note that,
because the definition of FSR is based on a sine wave, it is possible to support a square wave test signal
output whose level is +3 dBFS.
Total harmonic distortion (THD) The ratio of the RMS sum of the harmonic distortion products in the specified bandwidth (see note) relative
to the RMS amplitude of the fundamental (i.e., test frequency) output.
Signal-to-noise ratio (SNR)
A measure of the difference in level between the output response of a 1-kHz, 94 dB SPL sine wave and the
idle noise output.
Dynamic Range (DR)
The ratio of the 10% THD microphone output level (in response to a sine wave input) and the idle noise
output.
Note:
Unless otherwise specified, all performance measurements are specified with a low-pass brick-wall filter and, where noted, an
A-weighted filter. The low-pass filter removes out-of-band noise.
Parameter
Table 3-2. Recommended Operating Conditions
Parameter
Supply voltage
Ground
Clock frequency
Operating temperature range
Symbol
VDD
GND
F
CLK
T
A
Min
1.62
—
0.3
–40
Typ
1.8
0
—
—
Max
1.98
—
3.2
+85
Units
V
V
MHz
ºC
Table 3-3. Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits.
Device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified.
Symbol
Min
Max
Units
Supply voltage
VDD
–0.3
2.4
V
1
[2]
Input voltage
V
IN
–0.3
2.3
V
3
Input current
I
IN
–10
+10
mA
Operating temperature range
T
A
–40
+105
ºC
Storage temperature prior to soldering
T
Stgp
—
30
ºC
—
60
%
Storage relative humidity prior to soldering
RH
Stgp
Storage temperature after soldering
T
Stg
–40
+105
ºC
ESD-sensitive device. The CS7250B is manufactured on a CMOS process. It is therefore generically susceptible to damage from
excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. This device is
qualified to current JEDEC ESD standards
1
Parameter
1.All voltages are measured with respect to GND.
2.If VDD is above the minimum recommended operating level (see
Table 3-2),
the maximum input voltage is VDD + 0.3 V.
3.Input current is positive when flowing into the device.
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