TBD62789APG
TOSHIBA BiCD Integrated Circuit Silicon Monolithic
TBD62789APG
8-ch source type DMOS transistor array including D type flip-flop
TBD62789APG is a DMOS transistor array with 8 circuits including D type
flip flop logic circuits. Please be careful about thermal conditions during use.
Features
•
•
•
•
Built-in 8 circuits
High output voltage
High output current
Package
: V
OUT
= 50 V (max)
: I
OUT
= 500 mA/ch (max)
: DIP20-P-300-2.54A
DIP20-P-300-2.54A
Weight
:
1.4 g (typ.)
Pin Assignment (top view)
VDD
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
GND
/CLR
D1
D2
D3
D4
D5
D6
D7
D8
CLK
©2017 Toshiba Corporation
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TBD62789APG
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin name
/CLR
D1
D2
D3
D4
D5
D6
D7
D8
CLK
GND
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
VDD
Function
Input pin of clear signals
Input pin of data signals
Input pin of data signals
Input pin of data signals
Input pin of data signals
Input pin of data signals
Input pin of data signals
Input pin of data signals
Input pin of data signals
Input pin of clock signals
Ground pin
Output pin
Output pin
Output pin
Output pin
Output pin
Output pin
Output pin
Output pin
Power supply pin
Block Diagram
Y1
Clamp
diode
Clamp
diode
Y2
Clamp
diode
Y3
Clamp
diode
Y4
Clamp
diode
Y5
Clamp
diode
Y6
Clamp
diode
Y7
Clamp
diode
Y8
VDD
CLK
/CLR
D
100kΩ
(typ.)
100kΩ
(typ.)
CK
R
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
D
CK
R
Q
100kΩ
(typ.)
100kΩ
(typ.)
100kΩ
(typ.)
100kΩ
(typ.)
100kΩ
(typ.)
100kΩ
(typ.)
100kΩ
(typ.)
100kΩ
(typ.)
D1
D2
D3
D4
D5
D6
D7
Basic circuit may be omitted partially or simplified for explanatory purpose.
D8
GND
Function Table
INPUT
OUTPUT: Y
/CLR
CLK
D
L
X
X
Z (OFF)
H
↑
L
Z (OFF)
H
↑
H
H (ON)
H
L
X
Y0
H
↓
X
Y0
↑: Change from”L” to”H”
↓: Change from”H” to”L”
H: High level
Z: High impedance (OFF)
X: Don’t care
Y0: Y level immediately before determining the input condition shown in the table
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TBD62789APG
Absolute Maximum Ratings (Ta = 25°C)
Characteristics
Power supply voltage
Output current (per ch)
Input voltage
Clamp diode withstand voltage
Clamp diode forward current
Power dissipation
Operating temperature
Storage temperature
Symbol
V
DD
I
OUT
V
IN
V
R
I
F
P
D
(Note1)
T
opr
T
stg
Rating
50
-500
-0.5 to 6
50
500
1.76 (Note2)
-40
to 85
-55
to 150
Unit
V
mA
V
V
mA
W
°C
°C
Note1: On PCB (size: 50 mm × 50 mm × 1.6 mm, Cu area: 40 %, single-side glass epoxy)
Note2: When Ta exceeds 25 °C, it is necessary to do the derating with 14.1 mW/°C.
Operating Ranges (Ta = -40 to 85°C, unless otherwise specified)
Characteristics
Power supply voltage
Output current (per ch)
(Note)
Clamp diode forward current
Input voltage (Output on)
Input voltage (Output off)
Setup time
Hold time
Pulse width of CLK and /CLR
Clock frequency
Symbol
V
DD
Test conditions
―
1 circuit ON, Ta = 25 °C
I
OUT
t
pw
= 25 ms
8 circuits ON
Ta = 85 °C
T
j
= 120 °C
―
CLK pin, /CLR pin, and D1 to D8 pin
CLK pin, /CLR pin, and D1 to D8 pin
D setup time to CLK input
D hold time to CLK input
CLK pin and /CLR pin
CLK pin
Duty = 10 %
Duty = 50 %
Min
4.5
0
0
0
―
2.0
0
15
15
100
―
Typ.
―
―
―
―
―
―
―
―
―
―
―
Max
50
-400
-400
-195
400
5.5
0.8
―
―
―
5
mA
V
V
ns
ns
ns
MHz
mA
Unit
V
IF
V
IN (ON)
V
IN (OFF)
tsu
th
tw
fCLK
Note: Stand alone
Timing chart
CLK
50%
t
w
D
50%
t
su
t
h
50%
50%
Timing charts may be omitted partially or simplified for explanatory purposes.
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TBD62789APG
Electrical Characteristics (Ta = 25°C, unless otherwise specified)
Characteristics
Output leakage current
Symbol
I
leak
Test
Circuit
1
Test conditions
V
DD
= 50 V, Ta = 85 °C
At output OFF
I
OUT
= -350 mA
V
DD
= 10 V
Output voltage
(Output ON-resistance)
V
DS
(R
ON)
2
I
OUT
= -200 mA
V
DD
= 10 V
I
OUT
= -100 mA
V
DD
= 10 V
Input current (Output ON)
Input current (Output OFF)
Power supply current
Clamp diode leakage current
Clamp diode forward voltage
I
IN (ON)
I
IN(OFF)
I
CC(ON)
I
CC(OFF)
I
R
V
F
t
pHL
(CLK)
3
4
3
4
5
6
7
V
IN
= 5.5 V, V
DD
= 50 V
V
IN
= 0 V, V
DD
= 50 V
V
DD
=50 V, Output ON
V
DD
=50 V, Output OFF
V
R
= 50 V, Ta = 85 °C
I
F
= 350 mA
CLK (50%) to Y (50%)
Y changes from H to L.
C
L
=15pF, R
L
=25Ω
V
DD
= 10 V
CLK (50%) to Y (50%)
Y changes from L to H.
C
L
=15 pF, R
L
=25
Ω
V
DD
= 10 V
/CLR (50%) to Y (50%)
Y changes from H to L.
C
L
=15 pF, R
L
=25
Ω
V
DD
= 10 V
Min
Typ.
Max
1.0
1.14
(3.25)
0.65
(3.25)
0.325
(3.25)
100
1
40
40
1.0
2.0
200
μA
μA
mA
mA
μA
V
ns
V
(Ω)
Unit
μA
―
―
―
―
―
―
―
―
―
―
―
―
0.49
(1.4)
0.28
(1.4)
0.14
(1.4)
―
―
24
24
―
―
120
Propagation delay time
t
pLH
(CLK)
7
―
120
200
ns
t
pHL
(/CLR)
7
―
120
200
ns
Timing chart
CLK
50%
50%
Y
t
pHL(CLK)
/CLR
50%
50%
t
pLH(CLK)
50%
Y
t
pHL(/CLR)
50%
Timing charts may be omitted partially or simplified for explanatory purposes.
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TBD62789APG
Test Circuit
1. I
leak
PG
(Y = OFF)
D
CLK
/CLR
VDD
Y
GND
2. V
DS
(R
ON
)
PG
(Y = ON)
D
CLK
/CLR
VDD
Y
GND
V
DS
I
OUT
I
leak
V
DD
V
DD
R
ON
= V
DS
/ I
OUT
3. I
IN (ON)
and
I
CC (ON)
4. I
IN (OFF)
and
I
CC (OFF)
I
IN(ON)
I
IN(ON)
I
IN(ON)
V
IN
V
IN
D
CLK
/CLR
VDD
Y
GND
I
CC(ON)
V
DD
V
IN
V
IN
I
IN(OFF)
I
IN(OFF)
I
IN(OFF)
D
CLK
/CLR
VDD
Y
GND
I
CC(OFF)
V
DD
V
IN
V
IN
5. I
R
6. V
F
PG
(Y = OFF)
D
CLK
/CLR
VDD
Y
GND
PG
(Y = OFF)
I
R
V
R
D
CLK
/CLR
VDD
Y
GND
V
DD
I
F
V
F
V
DD
7. t
pHL (CLK)
, t
pLH (CLK)
, t
pHL (/CLR)
D
CLK
/CLR
VDD
Y
GND
PG
R
L
C
L
V
DD
Test circuits may be omitted partially or simplified for explanatory purpose.
Precautions for Using
This IC does not incorporate protection circuits for over current and over voltage.
Therefore, if the short-circuit between adjacent pins or between outputs, the short-to-power or ground fault has occurred,
the current or voltage beyond the absolute maximum rating is impressed, and IC may be destroyed. When designing,
please consider enough in power supply line, output line, and GND line.
In addition, so as not to continue to flow a current that exceeds the absolute maximum rating of the IC, please insert the
appropriate fuse in the power supply line.
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2017-04-26
嵌入式系统
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