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AUGUST 2005
ST78C36/36A
ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO
REV. 5.0.2
GENERAL DESCRIPTION
The ST78C36/36A is a monolithic Parallel Port
Interface for use with IBM PC compatible platforms.
Operation as a standard Centronics printer port is the
default, but software may re-configure the device to
support bi-directional IBM PS/2 parallel port,
Enhanced Parallel Port (EPP), or the Extended
Capabilities Port (ECP, as defined by Hewlett
Packard and Microsoft) modes. The ECP modes are
supported by a 16 byte FIFO that may be accessed
by programmed I/O or DMA cycles.
APPLICATIONS
•
Printers, Scanners and other peripherals
•
ZIP Drives and back up drives
•
Printer Server
•
Embedded Applications
FEATURES
•
IBM AT bus compatible
•
Bi-directional port capability
•
16 byte FIFO for ECP modes
•
On-chip oscillator (ST78C36A, ST78C36CQ64)
•
Software selectable Interrupt (5, 7, or 9) and 8-bit
DMA channel (ST78C36CQ64)
F
IGURE
1. ST78C36/36A B
LOCK
D
IAGRAM
D0-D7
-IOR
-IOW
RESET
Data bus
&
Control Logic
Printer
FIFO
Registers
Inter Connect Bus Lines
&
Control signals
Printer
Data
Ports
PD0-PD7
A0-A2
A10
-CS
AEN
-IOR, -IOW
-IRQx
IOCHRDY
DRQx
PDIR
TC
-DACKx
Register
Select
Logic
Printer
Control
Logic
-STROBE
INIT
-AUTOFDX
-SELCTIN
PE, SELECT
BUSY, -ACK
-ERROR
Clock
&
Timing
Generator
Interrupt
Control
Logic
XTAL2
XTAL1
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
ST78C36/36A
ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO
F
IGURE
2. ST78C36/36A P
IN
O
UT
A
SSIGNMENTS
-ERROR
BUSY
SLCT
DRQ1
DRQ2
xr
REV. 5.0.2
-ACK
-IOW
GND
-IOR
VCC
N.C.
50
PE
A1
64
63
62
61
60
59
58
57
56
55
54
53
52
A0
51
N.C.
-DACK2
DRQ3
-DACK3
D7
D6
D5
D4
D3
D2
D1
D0
AEN
-IRQ9
GND
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
49
48
47
46
45
44
43
42
N.C.
TC
GND
-DACK1
A2
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
GND
A10
N.C.
N.C.
N.C.
ST78C36CQ64
64-LQFP
41
40
39
38
37
36
35
34
33
IOCHRDY
-AUTOFDX
-STROBE
GND
-SLCTIN
N.C.
N.C.
XTAL1
XTAL2
PDIR
-ERROR
RESET
-IRQ5
-IRQ7
N.C.
INIT
-CS
-ACK
-ACK
-ERROR
BUSY
BUSY
SLCT
SLCT
-IOW
NOTE:
PINOUTS NOT TO SCALE. THE 64-LQFP
PACKAGE IS PHYSICALLY SMALLER THAN
THE 44-PLCC PACKAGE.
-IOW
-IOR
-IOR
VCC
VCC
PE
PE
TC
TC
A1
A0
A1
41
44
43
42
41
40
44
43
42
DRQ3
-DACK3
D7
D6
D5
D4
D3
D2
D1
D0
AEN
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
39
38
37
36
35
A2
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
GND
A10
DRQ3
-DACK3
D7
D6
D5
D4
D3
D2
D1
D0
AEN
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
40
39
38
37
36
35
6
5
4
3
2
1
6
5
4
3
2
1
A0
A2
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
GND
A10
ST78C36ACJ44
44-PLCC
34
33
32
31
30
29
ST78C36CJ44
44-PLCC
34
33
32
31
30
29
-STROBE
-STROBE
IOCHRDY
-SLCTIN
IOCHRDY
-AUTOFDX
-AUTOFDX
ORDERING INFORMATION
P
ART
N
UMBER
ST78C36CJ44
ST78C36ACJ44
ST78C36CQ64
P
ACKAGE
44-PLCC
44-PLCC
64-LQFP
O
PERATING
T
EMPERATURE
R
ANGE
0
o
C to 70
o
C
0
o
C to 70
o
C
0
o
C to 70
o
C
D
EVICE
S
TATUS
Active
Active
Active
2
-SLCTIN
RESET
CLOCK
RESET
XTAL1
XTAL2
GND
GND
-CS
-CS
-IRQ7
INIT
-IRQ7
PDIR
INIT
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REV. 5.0.2
ST78C36/36A
ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO
PIN DESCRIPTION
N
AME
44-
PLCC
PIN
#
64-
LQFP
PIN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A10
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
-IOR
-IOW
-CS
IOCHRDY
29
39
41
40
9
10
11
12
13
14
15
16
43
42
22
18
36
46
53
52
5
6
7
8
9
10
11
12
55
54
24
19
I
Address Select Lines. A10 places the ECP control/status/data ports at
0x400 offset from the -CS decoded address.
I/O
Data bus. Bi-directional data port.
I
I
I
O
Active low AT bus I/O Read strobe.
Chip select (active LOW). A LOW at this pin enables the parallel port /
CPU data transfer operation.
I/O Channel ready (internal pull-up / three stated active HIGH). This pin
goes low when the device requires addition clock cycles for read and
write.
Interrupt Request Lines (three stated active low).
-IRQ9
-IRQ7
-IRQ5
AEN
DRQ3
DRQ2
DRQ1
-DACK3
-DACK2
-DACK1
TC
-
19
-
17
7
-
-
8
-
-
6
14
20
18
13
3
63
51
4
2
47
62
O
I
O
DMA address enable (active HIGH). When this line is HIGH, the DMA
controller has control of the address bus.
Active high AT bus DMA ReQuest for channels 3, 2 and 1 (internal pull-
down three stated active HIGH). A request is generated by bringing a
DRQx line to a HIGH level. A DRQx line is held HIGH until the corre-
sponding DMA acknowledge “DACKx*” line goes LOW.
DMA Acknowledge signals for channels 3, 2 and 1 (internal pull-up /three
stated active low).
I
I
Terminal Count (active HIGH). The ST78C36 terminates the DMA channel
when a HIGH pulse is detected.
3
ST78C36/36A
ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO
xr
REV. 5.0.2
PIN DESCRIPTION
N
AME
44-
PLCC
PIN
#
64-
LQFP
PIN
#
T
YPE
D
ESCRIPTION
PRINTER PORT INTERFACE
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
-STROBE
38
37
36
35
34
33
32
31
25
45
44
43
42
41
40
39
38
27
I/O
Bi-directional parallel port (three-state) to transfer data in or out of the
ST78C36 parallel port. PD[7:0] are latched during output mode. Output
only for SPP and PPF modes, bi-directional for all other modes.
O
Data strobe output (internal pull-up / three stated active low). This output
indicates to the printer that valid data is available at the printer port (PD0-
PD7).
Automatic line feed (internal pull-up / three stated active low). When this
signal is low the printer should automatically line feed after each line is
printed.
Initialize line printer (internal pull-up / three stated active low). When this
signal is low, it causes the printer to be initialized.
Line printer select (internal pull-up / three stated active low). When this
signal is low, it selects the printer.
Line printer error (internal pull-up / active low). This is an output from the
printer to indicate an error by holding it low during error condition.
Line printer selected (internal pull-up / active high). This is an output from
the printer to indicate that the line printer has been selected.
Line printer busy (internal pull-up / active high). An output from the printer
to indicate printer is not ready to accept data.
Line printer acknowledge (internal pull-up / active low). This input is
pulsed low by the printer to indicate that data has been accepted success-
fully.
Line printer paper empty (internal pull-up / active high). An output from the
printer to indicate out of paper.
Printer port direction indicator. HIGH indicates device is in input mode,
LOW indicates output mode. (ST78C36CJ44 and ST78C36CQ64 only).
-AUTOFDX
26
28
O
INIT
-SLCTIN
-ERROR
SLCT
BUSY
-ACK
27
28
1
2
3
4
29
30
57
58
59
60
O
O
I
I
I
I
PE
PDIR
5
21
61
23
I
O
SYSTEM SIGNALS
CLOCK/
XTAL1
XTAL2
RESET
20
21
24
21
22
26
I
O
I
Crystal oscillator input (ST78C36ACJ44, ST78C36CQ64) or External
clock input (ST78C36CJ44), nominal 24 MHz.
Crystal oscillator output, nominal 24 MHz. ST78C36ACJ44 and
ST78C36CQ64 only.
System RESET ( active HIGH).
4
xr
REV. 5.0.2
ST78C36/36A
ECP/EPP PARALLEL PRINTER PORT WITH 16-BYTE FIFO
PIN DESCRIPTION
N
AME
VCC
GND
44-
PLCC
PIN
#
44
23,30
64-
LQFP
PIN
#
16, 56
15, 25,
37, 48,
64
T
YPE
Pwr
Pwr
Power Supply (+5V).
Supply Ground.
D
ESCRIPTION
1.0 OVERVIEW
This device is designed around the Hewlett Packard/Microsoft specification for Extended Capabilities Port
Protocol with “ECR mode 100” defined as Enhanced Parallel Port (EPP) mode. The internal timing engines
were designed around a 24 MHz reference, which can be supplied from an external source or by the built-in
oscillator circuit (ST78C36ACJ and ST78C36CQ64 only) with an appropriate crystal.
At system RESET, the device defaults to standard IBM PC compatible Centronics printer mode (output only).
The bi-directional PS/2, EPP, and ECP modes can only be activated by programming the ECR mode field (this
requires address bit A10 = 1, which is outside the normal ISA I/O space).
Optional capabilities of the ECP specification are set as follows:
■
■
■
■
■
■
■
ECP defined interrupts are pulsed, LOW true (Centronics -ACK is non-pulsed, LOW true).
PWord size is forced to 1 byte.
There is 1 byte in the transmitter that does not affect the FIFO full bit (ECP modes).
RLE compression is not supported in hardware.
IRQ channel is selectable as 5, 7, or 9 (ST78C36CQ64 only).
DMA channel is selectable as 1, 2, or 3 (ST78C36CQ64 only).
FIFO THRESHOLD is set at 8 (used only for non-DMA access to the FIFO).
PORT
DATA
ECP-AFIFO
DSR
DCR
EPP-APort
EPP-DPort
C-FIFO
ECP-DFIFO
T-FIFO
Cnfg-A
Cnfg-B
ECR
ADDRESS
000
000
001
002
003
004 - 007
400
400
400
400
401
402
R/W
R/W
W
R
R/W
R/W
R/W
W
R/W
R/W
R
R/W
R/W
MODE
000, 001
011
All
All
100
100
010
011
110
111
111
All
FUNCTION
Data Register
ECP FIFO (Address)
Status Register
Control Register
EPP Port (Address)
EPP Port (Data)
Parallel Port Data FIFO
ECP FIFO (Data)
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
5
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