74ACTQ541 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs
March 1993
Revised November 1999
74ACTQ541
Quiet Series Octal Buffer/Line Driver
with 3-STATE Outputs
General Description
The 74ACTQ541 is an octal buffer/line driver designed to
be employed as memory and address drivers, clock drivers
and bus oriented transmitter/receivers.
This device is similar in function to the 74ACTQ244 while
providing flow-through architecture (inputs on opposite side
from outputs). This pinout arrangement makes this device
especially useful as an output port for microprocessors,
allowing ease of layout and greater PC board density.
The 74ACTQ541 utilizes FACT Quiet Series technology
to guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series features GTO
output control and undershoot corrector in addition to split
ground bus for superior performance.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Inputs and outputs on opposite sides of package for
easy board layout
s
Non-inverting 3-STATE outputs
s
Guaranteed 4 kV minimum ESD immunity
s
TTL compatible inputs
s
Outputs source/sink 24 mA
Ordering Code:
Order Number
74ACTQ541SC
74ACTQ541MTC
74ACTQ541PC
Package Number
M20B
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the order code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Name
OE
1
– OE
2
I
0
–I
7
O
1
– O
7
Pin Description
3-STATE Output Enable (Active-LOW)
Inputs
Outputs
Truth Table
Inputs
OE
1
L
H
X
L
OE
2
L
X
H
L
Outputs
I
H
X
X
L
H
Z
Z
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
FACT, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
X
=
Immaterial
Z
=
High Impedance
© 1999 Fairchild Semiconductor Corporation
DS010932
www.fairchildsemi.com
74ACTQ541
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-up Source or Sink Current
Junction Temperature (T
J
)
±50
mA
−65°C
to
+150°C
±
300 mA
140°C
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
±50
mA
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−0.5V
to
+7.0V
Recommended Operating
Conditions
Supply Voltage V
CC
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate
∆V/∆t
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
3.0
4.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input Leakage Current
Maximum 3-STATE
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
1.1
−0.6
1.9
1.2
4.0
1.5
−1.2
2.2
0.8
0.6
0.002
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
2.99
4.49
2.0
2.0
0.8
0.8
2.9
4.4
3.86
4.86
0.1
0.1
0.36
0.36
±
0.1
±0.25
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
2.9
4.4
3.76
4.76
0.1
0.1
0.44
0.44
±
1.0
±2.5
1.5
75
−75
40.0
V
µA
µA
mA
mA
mA
µA
V
V
V
V
V
Units
V
V
V
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
(Note 2)
I
OH
=
−24
mA
−24
mA
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
(Note 2)
I
OH
= 24 mA
24 mA
V
I
=
V
CC
, GND
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
−
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Figure 1, Figure 2
(Note 4)(Note 5)
Figure 1, Figure 2
(Note 4)(Note 5)
(Note 4)(Note 6)
(Note 4)(Note 6)
V
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
Plastic DIP package.
Note 5:
Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 6:
Max number of Data Inputs (n) switching. (n–1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (V
ILD
),
0V to threshold (V
IHD
), f
=
1 MHz.
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2
74ACTQ541
AC Electrical Characteristics
V
CC
Symbol
Parameter
(V)
(Note 7)
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
OSHL
t
OSLH
Output to Output
Skew Data to Output (Note 8)
Output Disable Time
Propagation Delay
Data to Output
Output Enable Time
5.0
5.0
5.0
Min
2.0
2.0
2.0
2.0
1.5
1.5
T
A
= +25°C
C
L
=
50 pF
Typ
4.5
5.5
5.0
6.5
5.5
5.5
0.5
0.5
Max
7.0
7.0
9.0
9.0
7.5
7.5
1.0
1.0
Min
2.0
2.0
2.0
2.0
1.5
1.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Max
7.5
7.5
9.5
9.5
8.0
8.0
1.0
1.0
ns
ns
ns
ns
Units
Note 7:
Voltage Range 5.0 is 5.0V
±
0.5V
Note 8:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
70
Units
pF
pF
V
CC
=
OPEN
V
CC
=
5.0V
Conditions
3
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74ACTQ541
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500Ω.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
V
OLP
/V
OLV
and V
OHP
/V
OHV
:
• Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
• Measure V
OLP
and V
OLV
on the quiet output during the
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case active and enable transition.
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
ILD
and V
IHD
:
• Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
• First increase the input LOW voltage level, V
IL
, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
• Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
• Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability on the measurements.
V
OHV
and V
OLP
are measured with respect to ground reference.
Input pulses have the following characteristics: f
=
1 MHz, t
r
=
3 ns, t
f
=
3
ns, skew
<
150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
FIGURE 2. Simultaneous Switching Test Circuit
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4
74ACTQ541
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
5
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