74ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
June 1988
Revised October 1998
74ACT323
8-Bit Universal Shift/Storage Register with
Synchronous Reset and Common I/O Pins
General Description
The ACT323 is an 8-bit universal shift/storage register with
3-STATE outputs. Parallel load inputs and flip-flop outputs
are multiplexed to minimize pin count. Separate serial
inputs and outputs are provided for Q
0
and Q
7
to allow
easy cascading. Four operation modes are possible: hold
(store), shift left, shift right and parallel load.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Common parallel I/O for reduced pin count
s
Additional serial inputs and outputs for expansion
s
Four operating modes: shift left, shift right, load and
store
s
3-STATE outputs for bus-oriented applications
s
Outputs source/sink 24 mA
s
TTL-compatible inputs
Ordering Code:
Order Number
74ACT323PC
Package Number
N20A
Package Description
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
Pin Assignment
for DIP
Pin Descriptions
Pin Name
CP
DS
0
DS
7
S
0
, S
1
SR
OE
1
, OE
2
I/O
0
–I/O
7
Description
Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Synchronous Reset Input
3-STATE Output Enable Inputs
Multiplexed Parallel Data Inputs or
3-STATE Parallel Data Outputs
Q
0
, Q
7
FACT™ is a trademark of Fairchild Semiconductor Corporation.
Serial Outputs
© 1999 Fairchild Semiconductor Corporation
DS009787.prf
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74ACT323
Functional Description
The ACT323 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by S
0
and S
1
as shown
in the Mode Select Table. All flip-flop outputs are brought
out through 3-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
0
and Q
7
are also brought out on other pins for expansion in serial
shifting of longer words.
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All
other state changes are also initiated by the LOW-to-HIGH
CP transition. Inputs can change when the clock is in either
state provided only that the recommended setup and hold
times, relative to the rising edge of CP, are observed.
A HIGH signal on either OE
1
or OE
2
disables the 3-STATE
buffers and puts the I/O pins in the high impedance state.
In this condition the shift, load, hold and reset operations
can still occur. The 3-STATE buffers are also disabled by
HIGH signals on both S
0
and S
1
in preparation for a paral-
lel load operation.
Mode Select Table
Inputs
SR
L
H
H
H
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Response
CP
S
1
X
H
L
H
L
S
0
X
H
H
L
L
X
Synchronous Reset; Q
0
–Q
7
=
LOW
Parallel Load; I/O
n
→Q
n
Shift Right; DS
0
→Q
0
, Q
0
→Q
1
, etc.
Shift Left; DS
7
→Q
7
, Q
7
→Q
6
, etc.
Hold
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2
74ACT323
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74ACT323
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source or
Sink Current (I
O
)
DC V
CC
or Ground Current
Per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
±50
mA
−65°C
to
+150°C
±50
mA
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−0.5V
to
+7.0V
Junction Temperature (T
J
)
PDIP
140°C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (∆V/∆t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT™ circuits outside databook specifications.
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
DC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
V
IH
V
IL
V
OH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZT
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Maximum I/O
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.001
0.001
0.1
0.1
0.36
0.36
±0.1
±0.3
0.6
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
Units
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
I
OH
=
−24
mA
I
OH
=
−24
mA (Note 2)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
V
V
V
V
0.44
0.44
±1.0
±3.0
1.5
75
−75
V
µA
µA
mA
mA
mA
µA
I
OL
=
−24
mA
I
OL
=
−24
mA (Note 2)
V
I
=
V
CC
, GND
V
I/O
=
V
CC
or GND
V
IN
=
V
IH
, V
IL
V
I
=
V
CC
−
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
5.5
5.5
5.5
5.5
5.5
5.5
4.0
40.0
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4
74ACT323
AC Electrical Characteristics
V
CC
Symbol
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Maximum Input Frequency
Propagation Delay
CP to Q
0
or Q
7
Propagation Delay
CP to Q
0
or Q
7
Propagation Delay
CP to I/O
n
Propagation Delay
CP to I/O
n
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
3.5
3.5
4.0
3.0
7.5
7.5
8.5
8.0
11.0
11.5
12.5
11.5
3.0
3.0
3.0
2.5
12.5
13.0
13.5
12.5
ns
ns
ns
ns
5.0
6.0
10.0
14.5
5.0
16.0
ns
5.0
5.0
8.5
12.5
4.5
14.5
ns
5.0
5.0
9.0
13.5
4.5
15.0
ns
(V)
(Note 4)
5.0
5.0
Min
120
5.0
T
A
=
25°C
C
L
=
50 pF
Typ
125
9.0
12.5
Max
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
110
4.0
14.0
Max
MHz
ns
Units
Note 4:
Voltage Range 5.0 is 5.0V
±0.5V
AC Operating Requirements
T
A
=
25°C
Symbol
Parameter
V
CC
(V)
(Note 5)
t
S
Setup Time, HIGH or LOW
S
0
or S
1
to CP
t
H
Hold Time, HIGH or LOW
S
0
or S
1
to CP
t
S
Setup Time, HIGH or LOW
I/O
n
, DS
0
, DS
7
to CP
t
H
Hold Time, HIGH or LOW
I/O
n
, DS
0
, DS
7
to CP
t
S
Setup Time, HIGH or LOW
SR to CP
t
H
Hold Time, HIGH or LOW
SR to CP
t
W
CP Pulse Width
HIGH or LOW
Note 5:
Voltage Range 5.0 is 5.0V
±0.5V
T
A
= −40°C
to
+85°C
C
L
=
50 pF
V
CC
= +5.0V
Guaranteed Minimum
5.0
5.0
ns
Units
C
L
=
50 pF
V
CC
= +5.0V
Typ
2.0
5.0
5.0
0
1.5
1.5
ns
5.0
1.0
4.0
4.5
ns
5.0
0
1.0
1.0
ns
5.0
1.0
2.5
2.5
ns
5.0
0
1.0
1.0
ns
5.0
2.0
4.0
4.5
ns
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
170
Units
pF
pF
V
CC
=
OPEN
V
CC
=
5.0V
Conditions
5
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