Note e: These parameters are guaranteed but not tested.
42
STK12C68-IM
SRAM MEMORY OPERATION
READ CYCLES #1 & #2
SYMBOLS
NO.
1
2
3
4
5
6
7
8
9
10
11
#1, #2
t
ELQV
t
AVAV
t
AVQVg
t
GLQV
t
AXQX
t
ELQX
t
EHQZh
t
GLQX
t
GHQZh
t
ELICCHe
t
EHICCLc,e
Alt.
t
ACS
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
PARAMETER
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
25
0
10
0
35
5
5
10
0
17
0
45
25
25
10
5
5
17
0
20
STK12C68-25-IM
MIN
MAX
25
35
35
20
5
5
20
STK12C68-35-IM
MIN
MAX
35
45
45
25
(V
CC
= 5.0V
±
10%)
d
STK12C68-45-IM
MIN
MAX
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note c: Bringing E
≥
V
IH
will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
Note e: Parameter guaranteed but not tested.
Note f: For READ CYCLE #1 and #2, W is high for entire cycle.
Note g: Device is continuously selected with E low and G low.
Note h: Measured
±
200mV from steady state output voltage.
READ CYCLE #1
f,g
2
t
AVAV
ADDRESS
5
t
AXQX
DQ (Data Out)
3
t
AVQV
DATA VALID
READ CYCLE #2
f
2
t
AVAV
ADDRESS
1
t
ELQV
11
t
EHICCL
7
t
EHQZ
9
t
GHQZ
DATA VALID
E
t
ELQX
4
6
G
t
GLQV
8
t
GLQX
DQ (Data Out)
10
t
ELICCH
I
CC
ACTIVE
STANDBY
43
STK12C68-IM
WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
12
13
14
15
16
17
18
19
20
21
t
AVAV
t
WLWH
t
ELWH
t
DVWH
t
WHDX
t
AVWH
t
AVWL
t
WHAX
t
WLQZh,j
t
WHQX
#2
t
AVAV
t
WLEH
t
ELEH
t
DVEH
t
EHDX
t
AVEH
t
AVEL
t
EHAX
Alt.
t
WC
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold After End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
5
PARAMETER
MIN
25
20
20
10
0
20
0
0
10
5
MAX
MIN
35
30
30
18
0
30
0
0
17
MAX
STK12C68-25-IM
(V
CC
= 5.0V
±
10%)
d
STK12C68-35-IM
STK12C68-45-IM
UNITS
MIN
45
35
35
20
0
35
0
0
20
5
MAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note h: Measured
±200mV
from steady state output voltage.
Note i: E or W must be
≥V
IH
during address transitions.
Note j: If W is low when E goes low, the outputs remain in the high impedance state.
WRITE CYCLE #1:
W CONTROLLED
i
12
t
AVAV
ADDRESS
14
t
ELWH
E
18
17
t
AVWH
19
t
WHAX
t
AVWL
W
13
t
WLWH
15
t
DVWH
16
t
WHDX
DATA IN
20
t
WLQZ
DATA OUT
PREVIOUS DATA
DATA VALID
21
t
WHQX
HIGH IMPEDANCE
WRITE CYCLE #2:
E CONTROLLED
i
12
t
AVAV
ADDRESS
18
t
AVEL
E
17
t
AVEH
W
13
t
WLEH
15
t
DVEH
DATA IN
DATA VALID
14
t
ELEH
19
t
EHAX
16
t
EHDX
DATA OUT
HIGH IMPEDANCE
44
STK12C68-IM
NONVOLATILE MEMORY OPERATION
MODE SELECTION
E
H
L
L
L
W
X
H
L
H
HSB
H
H
H
H
A
12
- A
0
(hex)
X
X
X
0000
1555
0AAA
1FFF
10F0
0F0F
L
H
H
0000
1555
0AAA
1FFF
10F0
0F0E
X
X
L
X
MODE
Not Selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
I/O
Output High Z
Output Data
Input Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output High Z
I
CC2
/Standby
Active
POWER
Standby
Active
Active
Active
k,l
k,l
k,l
k,l
k,l
k
k,l
k,l
k,l
k,l
k,l
k
m
l
NOTES
STORE/Inhibit
Note k: The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a
STORE
cycle or (0000, 1555, 0AAA, 1FFF, 10F0,
0F0E) for a
RECALL
cycle. W must be high during all six consecutive cycles. See
STORE
cycle and
RECALL
cycle tables and diagrams for further details.
Note l: I/O state assumes that G
≤
V
IL
. Activation of nonvolatile cycles does not depend on the state of G.
Note m: HSB initiated
STORE
operation actually occurs only if a WRITE has been done since last
STORE
operation. After the
STORE
(if any) completes, the
part will go into standby mode inhibiting all operation until HSB rises.
HARDWARE
STORE
/RECALL
SYMBOLS
NO.
22
23
24
25
26
t
RECALL
t
STORE
t
DELAY
t
RECOVER
t
ASSERT
V
SWITCH
I
HSB_OL
I
HSB_OH
t
HLHH
t
HLQZ
t
HHQX
t
HLHX
PARAMETER
MIN
MAX
20
10
1
700
250
4.0
3
5
60
4.5
UNITS
µs
ms
µs
ns
ns
V
mA
µA
HSB = V
OL
, Note e, n
HSB = V
IL
, Note e, n
Note e
Note e
NOTES
Note o
V
CC
≥
4.5V
RECALL
Cycle Duration
STORE
Cycle Duration
HSB Low to Inhibit On
HSB High to Inhibit Off
External
STORE
Pulse Width
Low Voltage Trigger Level
HSB Output Low Current
HSB Output High Current
Note e: These parameters guaranteed but not tested.
Note n: HSB is an I/O that has a weak internal pullup; it is basically an open drain output. It is meant to allow up to 32 STK12C68-IMs to be ganged together for
simultaneous storing. Do not use HSB to pullup any external circuitry other than other STK12C68 HSB pins.
Note o: A RECALL cycle is initiated automatically at power up when V
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