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SII1127ACTU: 产品描述2 PORT HDMI1.3 RECEIVER WITH HDM; 产品类别其他集成电路（IC）消费电路; 文件大小2MB，共76页; 制造商Lattice(莱迪斯); 官网地址http://www.latticesemi.com

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SII1127ACTU概述

2 PORT HDMI1.3 RECEIVER WITH HDM

SII1127ACTU规格参数

参数名称	属性值
厂商名称	Lattice(莱迪斯)
包装说明	HTFQFP,
Reach Compliance Code	compliant
ECCN代码	EAR99
商用集成电路类型	CONSUMER CIRCUIT
JESD-30 代码	S-PQFP-G128
长度	14 mm
功能数量	1
端子数量	128
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	HTFQFP
封装形状	SQUARE
封装形式	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
座面最大高度	1.2 mm
最大供电电压 (Vsup)	1.26 V
最小供电电压 (Vsup)	1.14 V
表面贴装	YES
温度等级	COMMERCIAL
端子形式	GULL WING
端子节距	0.4 mm
端子位置	QUAD
宽度	14 mm
Base Number Matches	1

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SiI9127A/SiI1127A HDMI Receiver with Deep

Color Output

Data Sheet

SiI-DS-1059-D

May 2017

SiI9127A/SiI1127A HDMI Receiver with Deep Color Output

Data Sheet

Contents

Acronyms in This Document .................................................................................................................................................6

1. General Description ......................................................................................................................................................7

Inputs ..................................................................................................................................................................7

Digital Video Output ............................................................................................................................................7

Digital Audio Interface.........................................................................................................................................8

Consumer Electronic Control ..............................................................................................................................8

System Applications ............................................................................................................................................8

Package ...............................................................................................................................................................8

2. Product Family ..............................................................................................................................................................9

3. Functional Description ................................................................................................................................................10

TMDS Digital Cores ............................................................................................................................................10

Active Port Detection and Selection .............................................................................................................10

HDCP Decryption Engine/XOR Mask .................................................................................................................11

HDCP Embedded Keys ...................................................................................................................................12

Data Input and Conversion ................................................................................................................................12

Mode Control Logic .......................................................................................................................................12

Video Data Conversion and Video Output ....................................................................................................12

Deep Color Support.......................................................................................................................................13

xvYCC .............................................................................................................................................................13

3D Video Formats ..............................................................................................................................................13

Automatic Video Configuration ....................................................................................................................15

Audio Data Output Logic ...................................................................................................................................15

S/PDIF ............................................................................................................................................................15

S ..................................................................................................................................................................15

Control and Configuration .................................................................................................................................16

Register/Configuration Logic ........................................................................................................................16

C Serial Ports ...............................................................................................................................................16

EDID FLASH and RAM Block ..........................................................................................................................17

CEC Interface .................................................................................................................................................17

Standby and HDMI Port Power Supplies .......................................................................................................17

4. Electrical Specifications ..............................................................................................................................................19

Absolute Maximum Conditions .........................................................................................................................19

Normal Operating Conditions ...........................................................................................................................20

DC Specifications ...............................................................................................................................................21

Digital I/O Specifications ...............................................................................................................................21

DC Power Supply Pin Specifications ..............................................................................................................22

AC Specifications ...............................................................................................................................................24

Video Output Timings ...................................................................................................................................24

Audio Output Timings ...................................................................................................................................25

Miscellaneous Timings ..................................................................................................................................26

Interrupt Timings ..........................................................................................................................................26

5. Timing Diagrams .........................................................................................................................................................28

TMDS Input Timing Diagrams ............................................................................................................................28

Power Supply Control Timings ..........................................................................................................................28

Power Supply Sequencing .............................................................................................................................28

Reset Timings ....................................................................................................................................................29

Digital Video Output Timing Diagrams ..............................................................................................................29

Output Transition Times ...............................................................................................................................29

Output Clock to Output Data Delay ..............................................................................................................30

Digital Audio Output Timings ............................................................................................................................30

Calculating Setup and Hold Times for Video Bus ..............................................................................................32

24/30/36-Bit Mode .......................................................................................................................................32

www.latticesemi.com/legal.

All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1059-D

SiI9127A/SiI1127A HDMI Receiver with Deep Color Output

Data Sheet

12/15/18-Bit Dual-Edge Mode ...................................................................................................................... 33

Calculating Setup and Hold Times for I

S Audio Bus ......................................................................................... 34

6. Pin Diagram and Descriptions ..................................................................................................................................... 35

Pin Diagram ....................................................................................................................................................... 35

Pin Descriptions................................................................................................................................................. 36

Digital Video Output Data Pins ..................................................................................................................... 36

Digital Video Output Control Pins ................................................................................................................. 37

Digital Audio Output Pins.............................................................................................................................. 37

Configuration/Programming Pins ................................................................................................................. 38

HDMI Control Signal Pins .............................................................................................................................. 38

TMDS Differential Signal Pins........................................................................................................................ 39

Power and Ground Pins ................................................................................................................................ 39

Reserved and Not Connected Pins ................................................................................................................ 39

7. Video Path .................................................................................................................................................................. 40

HDMI Input Modes to SiI9127A/SiI1127A Output Modes ................................................................................ 41

HDMI RGB 4:4:4 Input Processing................................................................................................................. 41

HDMI YCbCr/xvYCC 4:4:4 Input Processing................................................................................................... 42

HDMI YCbCr/xvYCC 4:2:2 Input Processing................................................................................................... 43

SiI9127A/SiI1127A Output Mode Configuration ............................................................................................... 44

RGB and YCbCr 4:4:4 Formats with Separate Syncs ..................................................................................... 45

YC 4:2:2 Formats with Separate Syncs .......................................................................................................... 47

YC 4:2:2 Formats with Embedded Syncs ....................................................................................................... 50

YC Mux (4:2:2) Formats with Separate Syncs ............................................................................................... 53

YC Mux 4:2:2 Formats with Embedded Syncs ............................................................................................... 55

12/15/18-Bit RGB and YCbCr 4:4:4 Formats with Separate Syncs ................................................................ 57

8. I C Interfaces............................................................................................................................................................... 59

HDCP E-DDC / I

C Interface ............................................................................................................................... 59

Local I

C Interface ............................................................................................................................................. 60

Video Requirement for I

C Access ..................................................................................................................... 60

C Registers ...................................................................................................................................................... 60

9. Design Recommendations .......................................................................................................................................... 61

Power Control ................................................................................................................................................... 61

Power-on Sequencing ....................................................................................................................................... 61

Power Pin Current Demands......................................................................................................................... 61

HDMI Receiver DDC Bus Protection .................................................................................................................. 62

Decoupling Capacitors ...................................................................................................................................... 62

ESD Protection .................................................................................................................................................. 62

HDMI Receiver Layout ....................................................................................................................................... 63

EMI Considerations ........................................................................................................................................... 64

Typical Circuit .................................................................................................................................................... 65

Power Supply Decoupling ............................................................................................................................. 65

HDMI Port Connections ................................................................................................................................ 66

Digital Video Output Connections ................................................................................................................ 67

Digital Audio Output Connections ................................................................................................................ 68

Control Signal Connections ........................................................................................................................... 69

Layout................................................................................................................................................................ 70

TMDS Input Port Connections ...................................................................................................................... 70

10.

Package Information ............................................................................................................................................... 71

ePad Requirements ........................................................................................................................................... 71

PCB Layout Guidelines ...................................................................................................................................... 71

Package Dimensions .......................................................................................................................................... 72

Marking Specification ........................................................................................................................................ 73

Ordering Information ........................................................................................................................................ 73

References .......................................................................................................................................................................... 74

www.latticesemi.com/legal.

All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1059-D

SiI9127A/SiI1127A HDMI Receiver with Deep Color Output

Data Sheet

Standards Documents .....................................................................................................................................................74

Standards Groups ...........................................................................................................................................................74

Lattice Semiconductor Documents .................................................................................................................................74

Technical Support ...........................................................................................................................................................74

Revision History ..................................................................................................................................................................75

Figures

Figure 1.1. Digital Television System Diagram ......................................................................................................................7

Figure 3.1. Digital Television Receiver Block Diagram ........................................................................................................10

Figure 3.2. Functional Block Diagram .................................................................................................................................11

Figure 3.3. Default Video Processing Path ..........................................................................................................................14

Figure 3.4. I

C Register Domains .........................................................................................................................................16

Figure 3.5. Power Island .....................................................................................................................................................18

Figure 4.1. Test Point VCCTP for VCC Noise Tolerance Specification .................................................................................20

Figure 4.2. Audio Crystal Schematic ...................................................................................................................................25

Figure 4.3. SCDT and CKDT Timing from DE or RXC Inactive/Active ...................................................................................27

Figure 5.1. TMDS Channel-to-Channel Skew Timing ..........................................................................................................28

Figure 5.2. Power Supply Sequencing .................................................................................................................................28

Figure 5.3. RESET# Minimum Timings.................................................................................................................................29

Figure 5.4. Video Digital Output Transition Times ..............................................................................................................29

Figure 5.5. Receiver Clock-to-Output Delay and Duty Cycle Limits ....................................................................................30

Figure 5.6. I

S Output Timings ............................................................................................................................................30

Figure 5.7. S/PDIF Output Timings ......................................................................................................................................31

Figure 5.8. MCLK Timings ....................................................................................................................................................31

Figure 5.9. 24/30/36-Bit Mode Receiver Output Setup and Hold Times ............................................................................32

Figure 5.10. 12/15/18-Bit Mode Receiver Output Setup and Hold Times ..........................................................................33

Figure 6.1. Pin Diagram .......................................................................................................................................................35

Figure 7.1. Receiver Video and Audio Data Processing Paths ............................................................................................40

Figure 7.2. HDMI RGB 4:4:4 Input to Video Output Transformations ................................................................................41

Figure 7.3. HDMI YCbCr/xvYCC 4:4:4 Input to Video Output Transformations ..................................................................42

Figure 7.4. HDMI YCbCr/xvYCC 4:2:2 Input to Video Output Transformations ..................................................................43

Figure 7.5. 4:4:4 Timing Diagram ........................................................................................................................................46

Figure 7.6. YC Timing Diagram ............................................................................................................................................49

Figure 7.7. YC 4:2:2 Embedded Sync Timing Diagram ........................................................................................................52

Figure 7.8. YC Mux 4:2:2 Timing Diagram ...........................................................................................................................54

Figure 7.9. YC Mux 4:2:2 Embedded Sync Encoding Timing Diagram .................................................................................56

Figure 7.10. 18-Bit Output 4:4:4 Timing Diagram ...............................................................................................................57

Figure 7.11. 15-Bit Output 4:4:4 Timing Diagram ...............................................................................................................58

Figure 7.12. 12-Bit Output 4:4:4 Timing Diagram ...............................................................................................................58

Figure 8.1. I

C Byte Read .....................................................................................................................................................59

Figure 8.2. I

C Byte Write ....................................................................................................................................................59

Figure 8.3. Short Read Sequence ........................................................................................................................................59

Figure 9.1. Decoupling and Bypass Capacitor Placement ...................................................................................................62

Figure 9.2. Cut-out Reference Plane Dimensions ...............................................................................................................63

Figure 9.3. HDMI to Receiver Routing – Top View ..............................................................................................................64

Figure 9.4. Power Supply Decoupling and PLL Filtering Schematic ....................................................................................65

Figure 9.5. HDMI Port Connections Schematic ...................................................................................................................66

Figure 9.6. Digital Display Schematic ..................................................................................................................................67

Figure 9.7. Audio Output Schematic ...................................................................................................................................68

Figure 9.8. Controller Connections Schematic ....................................................................................................................69

Figure 9.9. TMDS Input Signal Assignments .......................................................................................................................70

Figure 10.1. 128-Pin TQFP Package Diagram ......................................................................................................................72

Figure 10.2. Marking Diagram of SiI9127A .........................................................................................................................73

Figure 10.3. Alternate Marking Diagram ............................................................................................................................73

www.latticesemi.com/legal.

All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1059-D

SiI9127A/SiI1127A HDMI Receiver with Deep Color Output

Data Sheet

Tables

Table 2.1. Summary of New Features ................................................................................................................................... 9

Table 3.1. Digital Video Output Formats ............................................................................................................................ 12

Table 3.2. Supported 3D Video Formats ............................................................................................................................. 14

Table 3.3. Default Video Processing ................................................................................................................................... 14

Table 3.4. AVI InfoFrame Video Path Details ...................................................................................................................... 15

Table 3.5. Digital Output Formats Configurable through Auto Output Format Register ................................................... 15

Table 3.6. Supported MCLK Frequencies ............................................................................................................................ 16

Table 5.1. Calculation of 24/30/36-Bit Output Setup and Hold Times ............................................................................... 32

Table 5.2. Calculation of 12/15/18-Bit Output Setup and Hold Times ............................................................................... 33

Table 5.3. I

S Setup and Hold Time Calculations ................................................................................................................ 34

Table 7.1. Translating HDMI Formats to Output Formats .................................................................................................. 41

Table 7.2. Output Video Formats ....................................................................................................................................... 44

Table 7.3. 4:4:4 Mappings .................................................................................................................................................. 45

Table 7.4. YC 4:2:2 Separate Sync Pin Mappings ................................................................................................................ 47

Table 7.5. YC 4:2:2 (Pass Through Only) Separate Sync Pin Mapping ................................................................................ 48

Table 7.6. YC 4:2:2 Embedded Sync Pin Mappings ............................................................................................................. 50

Table 7.7. YC 4:2:2 (Pass Through Only) Embedded Sync Pin Mapping ............................................................................. 51

Table 7.8. YC Mux 4:2:2 Mappings ..................................................................................................................................... 53

Table 7.9. YC Mux 4:2:2 Embedded Sync Pin Mapping ...................................................................................................... 55

Table 7.10. 12/15/18-Bit Output 4:4:4 Mappings .............................................................................................................. 57

Table 8.1. Control of the Default I

C Addresses with the CI2CA Pin ................................................................................... 60

Table 9.1. Maximum Power Domain Currents versus Video Mode.................................................................................... 61

www.latticesemi.com/legal.

All other brand or product names are

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

SiI-DS-1059-D

SII1127ACTU

SII1127ACTU概述

SII1127ACTU规格参数

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