NAU8501
NAU8501
Data Sheet
24-bit Stereo Audio ADC with Differential Microphone Inputs
Description
The NAU8501 is a low power, high quality audio input system for portable applications. In addition to precision
24-bit stereo ADCs, this device integrates a broad range of additional functions to simplify implementation of
complete audio systems. The NAU8501 includes low-noise stereo differential high gain microphone inputs with
wide range programmable amplifiers, separate line inputs, and an analog bypass/sidetone line level stereo output.
Advanced on-chip digital signal processing includes a limiter/ALC (Automatic Level Control), 5-band equalizer,
notch filter, and a high-pass filter for speech optimization and wind noise reduction. The digital interface can
operate as either a master or a slave. Additionally, an internal fractional-N PLL is available to accurately
generate any audio sample rate clock for the ADCs derived using any available system clock from 8MHz
through 33MHz.
The NAU8501 operates with analog supply voltages from 2.5V to 3.6V, while the digital core can operate as low
as 1.7V to conserve power. Internal control registers enable flexible power conserving modes, shutting down or
reducing power in sub-sections of the chip under software control.
The NAU8501 is specified for operation from -40°C to +85°C. AEC-Q100 & TS16949 compliant device is
available upon request.
emPowerAudio
™
Key Features
ADC: 90dB SNR and -80dB THD (“A” weighted)
Stereo differential input microphone amplifiers
Very wide range programmable input amplifier
Stereo line inputs with gain options and mixing
Stereo line outputs with gain control and mute
On-chip high resolution fractional-N PLL
Integrated DSP with specific functions:
5-band equalizer
High pass filter / wind noise reduction
Automatic level control / limiter
Programmable notch filter
Serial control interfaces with read/write capability
Standard audio interfaces: PCM and I
2
S
Supports any sample rate from 8kHz to 48kHz
Read/Write control register interface
Applications
Audio Recording Devices
Security Systems
Video and Still Cameras
Enhanced Audio Inputs for SOC products
Audio Input Accessory Products
Gaming Systems
NAU8501 Data Sheet Rev1.8
Page 1 of 80
Feb, 2014
NAU8501
NAU8501YG
LLIN
RLIN
LMICN
LMICP
RMICN
RMICP
Serial Control Interface
Digital Audio Interface
I
2
S
PCM
Stereo
Line Input
and
Microphone
Differential
Input
LADC
Input
Mixer
RADC
ADC Filter
Volume
Control
High Pass &
Notch Filters
5-Band
Stereo
Equalizer
and
3-D Audio
LLINOUT
RLINOUT
MICBIAS
Microphone
Bias
GPIO
PLL
2-wire
SPI
RLINOUT
LLINOUT
MICBIAS
Pinout
VDDA2
26
26
VDDA
VREF
27
27
VSSA
29
29
28
28
LMICP
LMICN
LLIN/GPIO2
25
25
32
32
31
31
30
30
n/c
1
2
3
4
5
6
7
8
12
14
10
11
13
15
16
9
24
24
23
23
VSSA2
n/c
n/c
n/c
n/c
n/c
MODE
SDIO
RMICP
RMICN
RLIN/GPIO3
NAU8501YG
32-lead QFN
RoHS
22
22
21
21
20
20
19
19
18
18
17
17
FS
BCLK
ADCOUT
n/c
MCLK
VSSD
CSB/GPIO1
VDDC
VDDB
SCLK
Part Number
NAU8501YG
Dimension
5 x 5 mm
Package
32-QFN
Package
Material
Pb-Free
NAU8501 Data Sheet Rev1.8
Page 2 of 80
Feb, 2014
NAU8501
Pin Descriptions
Pin #
1
2
3
4
5
6
Name
LMICP
LMICN
LLIN/GPIO2
RMICP
RMICN
RLIN/GPIO3
Type
Analog Input
Analog Input
Analog Input /
Digital I/O
Analog Input
Analog Input
Analog Input /
Digital I/O
Digital I/O
Digital I/O
Digital Output
Digital Input
Supply
Supply
Supply
Digital I/O
Digital Input
Digital I/O
Digital Input
Functionality
Left MICP Input (common mode)
Left MICN Input
Left Line Input / alternate Left MICP Input / GPIO2
Right MICP Input (common mode)
Right MICN Input
Right Line Input/ alternate Right MICP Input / Digital
Output
In 4-wire mode: Must be used for GPIO3
Digital Audio DAC and ADC Frame Sync
Digital Audio Bit Clock
Digital Audio ADC Data Output
Not internally connected
Master Clock Input
Digital Ground
Digital Core Supply
Digital Buffer (Input/Output) Supply
3-Wire MPU Chip Select or General Purpose I/O
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
3-Wire MPU Data Input / 2-Wire MPU Data I/O
Control Interface Mode Selection Pin
Not internally connected
Not internally connected
Not internally connected
Not internally connected
Not internally connected
Secondary analog ground connection for minimum noise
Not internally connected
Secondary analog power connection for minimum noise
Decoupling for Midrail Reference Voltage
Analog Ground
Right Line Level Output
Left Line Level Output
Analog Power Supply
Programmable Low Noise Supply for Microphone Biasing
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
FS
BCLK
ADCOUT
n/c
MCLK
VSSD
VDDC
VDDB
CSB/GPIO1
SCLK
SDIO
MODE
n/c
n/c
n/c
n/c
n/c
VSSA2
n/c
VDDA2
VREF
VSSA
RLINOUT
LLINOUT
VDDA
MICBIAS
Supply
Supply
Reference
Supply
Analog Output
Analog Output
Supply
Analog Output
Notes
1. The 32-QFN package includes a bulk ground connection pad on the underside of the chip. This bulk ground should be
thermally tied to the PCB as much as possible, and electrically tied to the analog ground (VSSA, pin 28).
2. Unused analog input pins should be left as no-connection.
3. Unused digital input pins should be tied to ground.
4. Pins designated as NC (Not Internally Connected) should be left as no-connection
NAU8501 Data Sheet Rev1.8
Page 3 of 80
Feb, 2014
NAU8501
Block Diagram
VDDB
14
VDDC
13
VSSD
12
VDDA
31
VSSA
28
VDDA2
26
VSSA2
24
Bypass
Buffer
LADC
MIX/BOOST
Bypass
Mute
30
LLINOUT
2
LMICN
1
-
+
LMICP
3
S
LADC
Output paths support -57dB through
+6dB gain in 1dB steps, with each
path having an independent mute and
output disable
LLIN
HPF
ALC Control
5
ALC
Notch
Filter
RMICN
4
-
+
RMICP
RLIN
6
S
RADC
VDDA
27
R
R
RADC
MIX/BOOST
5 Band EQ
3D
Outputs are line-level, able
to drive 1Vrms into 1k-ohms
VREF
32
MICBIAS
MICROPHONE
BIAS
Bypass
Buffer
Bypass
Mute
29
RLINOUT
PLL
8
AUDIO INTERFACE
(PCM/IIS)
7
9
11
CONTROL INTERFACE
(2-, 3- and 4-wire)
16
17
15
18
NAU8501
BCLK
FS ADCOUT
MCLK SCLK
SDIO
CSB/ MODE
GPIO1
Figure 1: NAU8501 Block Diagram
NAU8501 Data Sheet Rev1.8
Page 4 of 80
Feb, 2014
NAU8501
Electrical Characteristics
Conditions: VDDC = 1.8V, VDDA = VDDB = VDDA2 = 3.3V, MCLK = 12.288MHz, T
A
= +25°C, 1kHz signal, fs = 48kHz,
24-bit audio data, 64X oversampling rate, unless otherwise stated.
Parameter
Analog to Digital Converter (ADC)
Full scale input signal
1
Symbol
V
INFS
Comments/Conditions
Min
Typ
Max
Units
Vrms
dBV
dB
dB
dB
Vrms
dBV
dB
dB
dB
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
pF
µV
PGABST = 0dB
1.0
PGAGAIN = 0dB
0
Signal-to-noise ratio
SNR
Gain = 0dB, A-weighted
tbd
90
Total harmonic distortion
2
THD+N
Input = -3dB FS input
-80
tbd
Channel separation
1kHz input signal
103
Microphone Inputs (LMICP, LMICN, RMICP, RMICN, LLIN, RLIN) and Programmable Gain Amplifier (PGA)
Full scale input signal
1
PGABST = 0dB
1.0
PGAGAIN = 0dB
0
Programmable gain
-12
35.25
Programmable gain step size
Guaranteed Monotonic
0.75
Mute Attenuation
120
Input resistance
Inverting Input
PGA Gain = 35.25dB
1.6
PGA Gain = 0dB
47
PGA Gain = -12dB
75
Non-inverting Input
94
Line Inputs
Line Path Gain = +6dB
20
Line In Gain = 0dB
40
Line In Gain = -12dB
159
Input capacitance
10
PGA equivalent input noise
0 to 20kHz, Gain set to
120
35.25dB
Input Boost Mixer
Gain boost
Boost disabled
0
Boost enabled
20
Line Input to boost/mixer gain
-12
6
Line Input step size to boost/mixer
3
Microphone Bias
Bias voltage
V
MICBIAS
See Figure 3
0.50, 0.60,0.65, 0.70,
0.75, 0.85, or 0.90
Bias current source
I
MICBIAS
3
Output noise voltage
V
n
1kHz to 20kHz
14
dB
dB
dB
dB
VDDA
VDDA
mA
nV/√Hz
NAU8501 Data Sheet Rev1.8
Page 5 of 80
Feb, 2014
聊聊、笑笑、闹闹
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
