Si52212/Si52208/Si52204/Si52202 Data
Sheet
12/8/4/2-Output PCI-Express Gen 1/2/3/4 and SRIS Clock
Generator
The Si52212/08/04/02 are the industry's highest performance and lowest power PCI Ex-
press clock generator family for 1.5–1.8 V PCIe Gen1/2/3/4 and SRIS applications. The
Si52212, Si52208, and Si52204 can source twelve, eight, and four 100 MHz PCIe differ-
ential clock outputs, respectively, plus one 25 MHz LVCMOS reference clock output.
The Si52202 can source two 100 MHz PCIe clock outputs only. All differential clock out-
puts are compliant to PCIe Gen1/2/3/4 common clock and separate reference clock ar-
chitectures specifications.
The Si52212/08/04/02 feature individual hardware control pins for enabling and disa-
bling each output, spread spectrum enable/disable for EMI reduction, and frequency se-
lect to select 133 MHz or 200 MHz differential output frequencies. These features can
also be controlled via I
2
C.
The small footprint and low power consumption make this family of PCIe clock genera-
tors ideal for industrial and consumer applications.
For more information about PCI-Express, Silicon Labs' complete PCIe portfolio, applica-
tion notes, and design tools, including the Silicon Labs PCIe Clock Jitter Tool for PCI-
Express compliance, please visit the Silicon Labs
PCI Express Learning Center.
Applications
• Servers
• Storage
• Data Centers
• PCIe Add-on Cards
• Network Interface Cards (NIC)
• Graphics Adapter Cards
• Multi-function Printers
• Digital Single-Lens Reflex (DSLR) Cameras
• Digital Still Cameras
• Digital Video Cameras
• Docking Stations
KEY FEATURES OR KEY POINTS
• 12/8/4/2-output low-power, push-pull HCSL
compatible PCI-Express Gen 1, Gen 2,
Gen 3, Gen 4 and SRIS-compliant outputs
• Low jitter: 0.4 ps max
• Individual hardware control pins and I
2
C
controls for Output Enable, Spread
Spectrum Enable and Frequency Select
• Triangular spread spectrum for EMI
reduction, down spread 0.25% or 0.5%
• Internal 100 Ω or 85 Ω line matching
• Adjustable output slew rate
• Power down (PWRDNb) function supports
Wake-on LAN (except Si52202)
• One non-spread, LVMCOS reference clock
output (except Si52202)
• Frequency Select to select 133 MHz or
200 MHz (except Si52202)
• 25 MHz crystal input or clock input
• I
2
C support with readback capabilities
• Extended temperature: –40 to 85 °C
• 1.5–1.8 V power supply, with separate
VDD and VDD_IO
• Small QFN packages
• Pb-free, RoHS-6 compliant
silabs.com
| Building a more connected world.
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Preliminary Rev. 0.7
Si52212/Si52208/Si52204/Si52202 Data Sheet
Feature List
1. Feature List
• 12/8/4/2-output 100 MHz PCIe Gen1/2/3/4 and SRIS compliant clock generator, with push-pull HCSL output drivers
• High port count with push-pull HCSL outputs to support highly integrated solution, eliminating external resistors for the HCSL out-
put drivers
• Low jitter of 0.4 ps max to meet PCIe Gen4 specifications with design margin
• Low power consumption.
• Lowest power consumption in the industry for a 2-output PCIe clock generator
• Individual hardware control pins and I
2
C controls for Output Enable, Spread Spectrum Enable and Frequency Select
• Output Enable function easily disables unused outputs for power saving
• Spread Enable function to turn on/off spread spectrum and to select spread levels, either down spread 0.25% or 0.5%
• Frequency Select function to select output frequency of 100 MHz, 133 MHz, or 200 MHz (except Si52202 where the output fre-
quency is limited to 100 MHz. Please contact Silicon Labs for 133 MHz or 200 MHz in Si52202)
• All above functions are controlled by individual hardware pins or I
2
C
• Internal 100 Ω or 85 Ω line matching
• Eliminates external line matching resistor to reduce board space
• Adjustable slew rate to improve signal quality for different applications and board designs
• Power down (PWRDNb) function supports Wake-on LAN (except Si52202)
• One non-spread, 25 MHz LVMCOS reference clock output (except Si52202)
• A buffered 25 MHz LVCMOS clock output to drive ASICS or SoCs on board
• 25 MHz reference input
• Supports a standard crystal or clock input for flexibility
• I
2
C support with readback capabilities
• 1.5–1.8 V power supply with separate VDD and VDD_IO
• Temperature range: –40 °C to 85 °C
• Small QFN packages to optimize board space. Smallest 2-output PCIe clock generator in the industry
• 64-pin QFN (9 x 9 mm) : 12-output
• 48-pin QFN (6 x 6 mm) : 8-output
• 32-pin QFN (5 x 5 mm) : 4-output
• 20-pin QFN (3 x 3 mm) : 2-output
• Pb-free, RoHS-6 compliant
silabs.com
| Building a more connected world.
Preliminary Rev. 0.7 | 2
Si52212/Si52208/Si52204/Si52202 Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Si522x Ordering Guide
Number of Outputs
Internal Termination
100 Ω
12-output
85 Ω
Part Number
Si52212-A01AGM
Si52212-A01AGMR
Si52212-A02AGM
Si52212-A02AGMR
Si52208-A01AGM
Si52208-A01AGMR
Si52208-A02AGM
Si52208-A02AGMR
Si52204-A01AGM
Si52204-A01AGMR
Si52204-A02AGM
Si52204-A02AGMR
Si52202-A01AGM
Si52202-A01AGMR
Si52202-A02AGM
Si52202-A02AGMR
Package Type
64-QFN
64-QFN - Tape and Reel
64-QFN
64-QFN - Tape and Reel
48-QFN
48-QFN - Tape and Reel
48-QFN
48-QFN - Tape and Reel
32-QFN
32-QFN - Tape and Reel
32-QFN
32-QFN - Tape and Reel
20-QFN
20-QFN - Tape and Reel
20-QFN
20-QFN - Tape and Reel
Temperature
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
100 Ω
8-output
85 Ω
100 Ω
4-output
85 Ω
100 Ω
2-output
85 Ω
2.1 Technical Support
Table 2.2. Technical Support URLs
Frequently Asked Questions
PCIe Clock Jitter Tool
PCIe Learning Center
Development Kit
www.silabs.com/Si522xx-FAQ
www.silabs.com/products/timing/pci-express-learning-center
www.silabs.com/products/timing/pci-express-learning-center
www.silabs.com/products/development-tools/timing/clock/si52204-evb-evaluation-kit.html
silabs.com
| Building a more connected world.
Preliminary Rev. 0.7 | 3
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. 3
2.1 Technical Support .
3. Functional Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Crystal Recommendations .
5.2 Crystal Loading .
.
.
.
.
5.3 Calculating Load Capacitors
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
19
.19
.19
.20
.21
.21
.21
.21
.21
.21
.22
5.4 PWRGD/PWRDNb (Power Down) Pin .
5.5 PWRDNb (Power Down) Assertion .
5.7 OEb Pin .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
5.6 PWRDNb (Power Down) Deassertion .
5.8 OEb Assertion .
5.10 FS Pin .
.
.
5.9 OEb Deassertion .
6. Test and Measurement Setup
7. PCIe Clock Jitter Tool
. . . . . . . . . . . . . . . . . . . . . . . . 23
. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
26
.26
.26
.26
.27
.27
.27
.28
.29
.31
.31
.34
.37
.40
8. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1 I
2
C Interface .
8.3 Block Read .
8.4 Block Write .
8.6 Byte Read
8.7 Byte Write
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
8.2 Block Read/Write .
8.5 Byte Read/Write
8.8 Data Protocol
8.9 Register Tables. . .
8.9.1 Si52212 Registers
8.9.2 Si52208 Registers
8.9.3 Si52204 Registers
8.9.4 Si52202 Registers
9. Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.43
.46
9.1 Si52212 Pin Descriptions
9.2 Si52208 Pin Descriptions
silabs.com
| Building a more connected world.
Preliminary Rev. 0.7 | 4
9.3 Si52204 Pin Descriptions
9.4 Si52202 Pin Descriptions
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.49
.51
10. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
10.1 Si52212 Package
10.3 Si52208 Package
10.5 Si52204 Package
10.7 Si52202 Package
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.53
.54
.56
.57
.59
.61
.62
.64
.66
.67
.68
.69
10.2 Si52212 Land Pattern .
10.4 Si52208 Land Pattern .
10.6 Si52204 Land Pattern .
10.8 Si52202 Land Pattern .
10.9 Si52212 Top Markings .
10.10 Si52208 Top Markings
10.11 Si52204 Top Markings
10.12 Si52202 Top Markings
11. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1 Revision 0.7 .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
70
.70
silabs.com
| Building a more connected world.
Preliminary Rev. 0.7 | 5
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
