电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

SY100E241JCTR

产品描述8-BIT SCANNABLE REGISTER
产品类别逻辑    逻辑   
文件大小59KB,共4页
制造商Microchip(微芯科技)
官网地址https://www.microchip.com
下载文档 详细参数 选型对比 全文预览

SY100E241JCTR概述

8-BIT SCANNABLE REGISTER

SY100E241JCTR规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Microchip(微芯科技)
包装说明PLASTIC, LCC-28
Reach Compliance Code_compli
其他特性HOLD MODE
计数方向RIGHT
系列100E
JESD-30 代码S-PQCC-J28
JESD-609代码e0
逻辑集成电路类型PARALLEL IN PARALLEL OUT
最大频率@ Nom-Su700000000 Hz
位数8
功能数量1
端子数量28
最高工作温度85 °C
最低工作温度
输出特性OPEN-EMITTER
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码QCCJ
封装等效代码LDCC28,.5SQ
封装形状SQUARE
封装形式CHIP CARRIER
电源-4.5 V
最大电源电流(ICC)173 mA
传播延迟(tpd)1 ns
认证状态Not Qualified
表面贴装YES
技术ECL
温度等级OTHER
端子面层Tin/Lead (Sn/Pb)
端子形式J BEND
端子节距1.27 mm
端子位置QUAD
触发器类型POSITIVE EDGE
最小 fmax900 MHz

文档预览

下载PDF文档
8-BIT SCANNABLE
REGISTER
SY10E241
SY100E241
FEATURES
s
1000ps max. CLK to output
s
Extended 100E V
EE
range of –4.2V to –5.5V
s
s
s
s
SHIFT overrides HOLD, /LOAD control
Asynchronous Master Reset
Pin-compatible with E141
Fully compatible with industry standard 10KH,
100K ECL levels
s
Internal 75K
input pulldown resistors
s
Fully compatible with Motorola MC10E/100E241
s
Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E241 are 8-bit shiftable registers designed
for use in new, high-performance ECL systems. Unlike the
E141, the E241 features internal data feedback organized
such that the SHIFT control overrides the HOLD, /LOAD
control. Thus, the normal operations of HOLD and LOAD
can be toggled with a single control line without the need for
external gating. This configuration also enables switching
to scan mode with the single SHIFT control line.
The eight inputs D
0
–D
7
accept parallel input data, while
S-IN accepts serial input data when in shift mode. Data is
accepted a set-up time before the rising edge of CLK.
Shifting is also accomplished on the rising clock edge. A
HIGH on the Master Reset pin (MR) asychronously resets
all the registers to zero.
BLOCK DIAGRAM
S-IN
D
D
0
Q
R
Q
0
PIN CONFIGURATION
D
5
V
CCO
SEL
0
NC
D
7
D
6
Q
7
25 24 23 22 21 20 19
SEL
1
CLK
MR
V
EE
S-IN
D
0
D
1
26
27
28
1
2
3
4
5
6
7
8
9
10 11
18
17
Q
6
Q
5
V
CC
NC
V
CCO
Q
4
Q
3
D
D
1
– D
6
Q
R
Q
1
– Q
6
TOP VIEW
PLCC
J28-1
16
15
14
13
12
BITS 1-6
D
2
D
3
D
D
7
SEL
1
(HOLD/LOAD)
SEL
0
(SHIFT)
CLK
MR
Q
R
Q
7
PIN NAMES
Pin
D
0
–D
7
S-IN
SEL
0
SEL
1
CLK
MR
Q
0
–Q
7
V
CCO
Function
Parallel Data Inputs
Serial Data Input
SHIFT Control
HOLD, /LOAD Control
Clock
Master Reset
Data Outputs
V
CC
to Output
V
CCO
Q
0
Q
1
Q
2
Rev.: C
D
4
Amendment: /1
1
Issue Date: February, 1998

SY100E241JCTR相似产品对比

SY100E241JCTR SY10E241JC SY10E241JCTR SY10E241 SY100E241JC
描述 8-BIT SCANNABLE REGISTER 8-BIT SCANNABLE REGISTER 8-BIT SCANNABLE REGISTER 8-BIT SCANNABLE REGISTER 8-BIT SCANNABLE REGISTER

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 41  2084  597  2102  698  16  56  45  54  55 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved