system. Utilizing an integrated system in a package (SiP)
technology, it includes a dual high-speed 14-bit A/D con-
verter, matching network, anti-aliasing filter and two low
noise, differential amplifiers. It is designed for digitizing
wide dynamic range signals with an intermediate frequency
(IF) up to 300MHz. The amplifiers allow either AC- or DC-
coupled input drive. Lowpass or bandpass filter networks
can be implemented with various bandwidths. Contact
Linear Technology regarding customization.
The LTM9002 is perfect for demanding communications
applications, with AC performance that includes 66dB SNR
and 76dB spurious free dynamic range (SFDR). Auxiliary
DACs allow gain balancing between channels.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.3V logic.
An optional multiplexer allows both channels to share a
digital output bus. Two single-ended CLK inputs can be
driven together or independently. An optional clock duty
cycle stabilizer allows high performance at full speed for
a wide range of clock duty cycles.
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
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Integrated Dual 14-Bit, High-Speed ADC, Passive
Filters and Fixed Gain Differential Amplifiers
Up to 300MHz IF Range
Lowpass and Bandpass Filter Versions
Integrated Low Noise, Low Distortion Amplifiers
Fixed Gain: 8dB, 14dB, 20dB or 26dB
50Ω, 200Ω or 400Ω Input Impedance
Integrated Bypass Capacitance, No External
Components Required
66dB SNR Up to 140MHz Input (LTM9002-AA)
76dB SFDR Up to 140MHz Input (LTM9002-AA)
Auxiliary 12-Bit DACs for Gain Adjustment
Clock Duty Cycle Stabilizer
Single 3V to 3.3V Supply
Low Power: 1.3W (665mW/ch.)
Shutdown and Nap Modes
15mm
×
11.25mm LGA Package
APPLICATIONS
n
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Telecommunications
Direct Conversion Receivers
Main and Diversity Receivers
Cellular Base Stations
TYPICAL APPLICATION
Dual Channel IF Receiver
V
CC
= 3V
V
DD
OV
DD
0.5V TO 3.6V
64k Point FFT, f
IN
= 15MHz, –1dBFS,
SENSE = V
DD
, Channel A (LTM9002-LA)
0
–10
–20
AMPLITUDE (dBFS)
–30
V
REF
INA
+
MAIN
RF
LO
DAC
DIFFERENTIAL
AMPLIFIERS
DAC
INB
+
DIVERSITY
RF
LO
9002 TA01
SAW
INA
–
FILTER
14-BIT
125Msps ADC
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5
10
15
20
25
FREQUENCY (MHz)
30
9002 TA01b
CLKOUT
ADC CLK
SPI
MUX
OF
SAW
INB
–
FILTER
14-BIT
125Msps ADC
OGND
GND
9002f
1
LTM9002
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PIN CONFIGURATION
SENSEB SENSEA
ALL OTHERS = GND
J
Supply Voltage (V
CC
) ................................ –0.3V to 3.6V
Supply Voltage (V
DD
, OV
DD
)......................... –0.3V to 4V
Digital Output Ground Voltage (OGND) ........ –0.3V to 1V
Input Current (IN
+
, IN
–
)........................................±10mA
DAC Digital Input Voltage
(CS/LD, SDI, SCK) ................................... –0.3V to 6V
Digital Input Voltage
(Except AMPSHDN) ................. –0.3V to (V
DD
+ 0.3V)
Digital Input Voltage
(AMPSHDN)..............................–0.3V to (V
CC
+ 0.3V)
Digital Output Voltage ................–0.3V to (OV
DD
+ 0.3V)
Operating Temperature Range
LTM9002C................................................ 0°C to 70°C
LTM9002I.............................................–40°C to 85°C
Storage Temperature Range...................–65°C to 125°C
INA
+
INA
–
V
CC
H
G
F
E
D
OV
DD
OGND
V
DD
OGND
INB
–
INB
+
C
B
A
1
2
3
4
5
6
7
8
9
10
11
12
OV
DD
CLKA CLKB
CONTROL
DATA
LGA PACKAGE
108-LEAD (15mm × 11.25mm × 2.32mm)
T
JMAX
= 125°C,
θ
JA
= 19°C/W,
θ
JCTOP
= 16°C/W,
θ
JCBOT
= 6°C/W
θ
JA
DERIVED FROM 101.5mm
×
114.5mm PCB WITH 4 LAYERS
WEIGHT = 0.935g
ORDER INFORMATION
LEAD FREE FINISH
LTM9002CV-AA#PBF
LTM9002CV-LA#PBF
LTM9002IV-AA#PBF
LTM9002IV-LA#PBF
TRAY
LTM9002CV-AA#PBF
LTM9002CV-LA#PBF
LTM9002IV-AA#PBF
LTM9002IV-LA#PBF
PART MARKING*
LTM9002VAA
LTM9002VLA
LTM9002VAA
LTM9002VLA
PACKAGE DESCRIPTION
108-Lead (15mm
×
11.25mm
×
2.3mm) LGA
108-Lead (15mm
×
11.25mm
×
2.3mm) LGA
108-Lead (15mm
×
11.25mm
×
2.3mm) LGA
108-Lead (15mm
×
11.25mm
×
2.3mm) LGA
TEMPERATURE RANGE
0°C to 70°C
0°C to 70°C
–40°C to 85°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to:
http://www.linear.com/packaging/
9002f
2
LTM9002
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. Unless otherwise noted. (Note 3)
SYMBOL
G
DIFF
PARAMETER
Gain
CONDITIONS
DC, LTM9002-AA
f
IN
= 140MHz
Channel A, DC (LTM9002-LA)
f
IN
= 15MHz
Channel B, DC (LTM9002-LA)
f
IN
= 15MHz
G
TEMP
V
IN
Gain Temperature Drift
Gain Matching
Input Voltage Range for –1dBFS
V
IN
= MAX, (Note 3)
External Reference
Both Channels, f
IN
= 140MHz (LTM9002-AA)
Channel A, f
IN
= 15MHz (LTM9002-LA)
Channel B, f
IN
= 15MHz (LTM9002-LA)
V
INCM
R
INDIFF
Input Common Mode Voltage Range
Differential Input Impedance
Both Channels (LTM9002-AA)
Channel A (LTM9002-LA)
Channel B (LTM9002-LA)
C
INDIFF
V
OS
Differential Input Capacitance
Offset Error (Note 5)
Offset Matching
Offset Drift
CMRR
I
SENSE
I
MODE
t
AP
t
JITTER
Common Mode Rejection Ratio
SENSE Input Leakage
MODE Input Leakage
Sample and Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Time Jitter
0V < SENSE < 1V
0V < MODE < V
DD
l
l
l
l
l
ELECTRICAL CHARACTERISTICS
MIN
25
19.4
7.5
TYP
26
25
20
19
8
7
1.5
5
100
200
800
MAX
27
20.6
8.5
UNITS
dB
dB
dB
dB
dB
dB
mdB/°C
mdB
mV
P-P
mV
P-P
mV
P-P
1
50
200
400
1
l
1.5
V
Ω
Ω
Ω
pF
Includes Parasitic
Including Amplifier and ADC
Including Amplifier and ADC
–3
–3
–5
0.3
0.3
±10
50
5
mV
mV
μV/°C
dB
3
3
0
0.2
μA
μA
ns
ps
RMS
CONVERTER CHARACTERISTICS
SYMBOL
ADC Characteristics
Resolution (No Missing Codes)
INL
DNL
Integral Linearity Error (Note 4)
Differential Linearity Error
PARAMETER
The
l
indicates specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 3)
CONDITIONS
LTM9002-AA
LTM9002-LA
LTM9002-AA
LTM9002-LA
LTM9002-AA
LTM9002-LA
l
l
l
l
MIN
14
12
TYP
MAX
UNITS
Bits
Bits
±1.5
±0.3
–1
–1
±0.6
±0.2
1
1
LSB
LSB
LSB
LSB
9002f
3
LTM9002
DYNAMIC ACCURACY
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
The
l
indicates specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. Input = –1dBFS. (Note 3)
CONDITIONS
70MHz Input (Both Channels), LTM9002-AA
140MHz Input (Both Channels), LTM9002-AA
15MHz Input (Channel A), LTM9002-LA
15MHz Input (Channel B), LTM9002-LA
l
l
l
l
l
l
l
l
l
l
l
l
MIN
61.5
67.7
68.5
67.5
75
72.7
74.2
78.8
79.8
60.7
67.1
67.9
TYP
66
66
69.9
71.1
82
76
86.2
85.5
90
90
88.5
90.7
66
66
69.7
70.8
77
73
77
–110
–110
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dB
dB
SFDR
Spurious Free Dynamic Range, 2nd or 3rd
Harmonic
70MHz Input (Both Channels), LTM9002-AA
140MHz Input (Both Channels), LTM9002-AA
15MHz Input (Channel A), LTM9002-LA
15MHz Input (Channel B), LTM9002-LA
SFDR
Spurious Free Dynamic Range 4th or Higher
70MHz Input (Both Channels), LTM9002-AA
140MHz Input (Both Channels), LTM9002-AA
15MHz Input (Channel A), LTM9002-LA
15MHz Input (Channel B), LTM9002-LA
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
70MHz Input (Both Channels), LTM9002-AA
140MHz Input (Both Channels), LTM9002-AA
15MHz Input (Channel A), LTM9002-LA
15MHz Input (Channel B), LTM9002-LA
IMD3
Third Order Inter-Modulation Distortion;
1MHz Tone Spacing, Two Tones –7dBFS
Crosstalk
70MHz Input, LTM9002-AA
140MHz Input, LTM9002-AA
15MHz Input, LTM9002-LA
140MHz Input, LTM9002-AA
15MHz Input, LTM9002-LA
AUXILIARY DAC CHARACTERISTICS
PARAMETER
Resolution
Monotonicity
Full-Scale Range
Settling Time
Internal Reference
±0.024% (±1LSB at 12 Bits),
No External Sense Capacitor
CONDITIONS
The
l
indicates specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Not applicable for LTM9002-LA) (Note 3)
MIN
l
l
TYP
MAX
UNITS
Bits
Bits
12
12
1.5
83.5
V
μs
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C.
SYMBOL
V
IH
V
IL
I
IN
C
IN
PARAMETER
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
CONDITIONS
V
DD
= 3V
V
DD
= 3V
V
IN
= 0V to V
DD
(Note 6)
l
l
l
DIGITAL INPUTS AND OUTPUTS
MIN
2
TYP
MAX
UNITS
V
Logic Inputs (CLK,
OE,
ADCSHDN, MUX,
CS/LD,
SCK, SDI)
0.8
–10
3
10
V
μA
pF
9002f
4
LTM9002
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C.
SYMBOL
V
IL
V
IH
I
IL
I
IH
Logic Outputs
OV
DD
= 3V
C
OZ
I
SOURCE
I
SINK
V
OH
V
OL
OV
DD
= 2.5V
V
OH
V
OL
OV
DD
= 1.8V
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
I
O
= –200μA
I
O
= 1.6mA
1.79
0.1
V
V
High Level Output Voltage
Low Level Output Voltage
I
O
= –200μA
I
O
= 1.6mA
2.49
0.09
V
V
Hi-Z Output Capacitance
Output Source Current
Output Sink Current
High Level Output Voltage
Low Level Output Voltage
OE
= 3V (Note 6)
V
OUT
= 0V
V
OUT
= 3V
I
O
= –10μA
I
O
= –200μA
I
O
= 10μA
I
O
= 1.6mA
l
l
DIGITAL INPUTS AND OUTPUTS
PARAMETER
Low Level Input Voltage
High Level Input Voltage
Input Low Current
Input High Current
CONDITIONS
l
l
MIN
TYP
MAX
0.8
UNITS
V
V
μA
μA
Logic Inputs (AMPSHDN)
2.4
0.5
1.4
3
AMPSHDN = 0.8V
AMPSHDN = 2.4V
l
l
3
50
50
2.7
2.995
2.99
0.005
0.09
0.4
pF
mA
mA
V
V
V
V
The
l
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 7)
SYMBOL PARAMETER
V
CC
V
DD
O
VDD
I
CC
Amplifier and Auxiliary DAC
Operating Supply Range
ADC Analog Supply Voltage
Output Supply Voltage
Amplifier
DAC Powered Up, Both Amplifiers Enabled, LTM9002-AA
Both Amplifiers Enabled, LTM9002-LA
I
CC(SHDN)
Amplifier Shutdown Supply Current
I
DD(ADC)
ADC Supply Current
AMPSHDN = 3V, DAC Powered Down
LTM9002-AA
LTM9002-LA
P
D(SHDN)
ADC Shutdown Power (Each Channel) ADCSHDN = AMPSHDN = 3V,
OE
= 3V, No CLK
P
D(NAP)
P
D(AMP)
P
D(ADC)
ADC Nap Mode Power (Each Channel) ADCSHDN = AMPSHDN = 3V,
FPGA/CPLD
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