204Pin DDR3 1.5V 1600 SO-DIMM
1GB Based on 128Mx16
AQD-SD31GN16-HC
Description
DDR3 SO-DIMM is high-speed, low power memory
module that use 128Mx16bits DDR3 SDRAM in FBGA
package and a 2048 bits serial EEPROM on a 204-pin
printed circuit board. DDR3 1.35V SO-DIMM is a Dual
In-Line Memory Module and is intended for mounting into
204-pin edge connector sockets.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Pin Identification
Symbol
A0~A15, BA0~BA2
DQ0~DQ63
DQS0~DQS7
/DQS0~/DQS7
CK0, /CK0,CK1, /CK1
CKE0, CKE1
ODT0, ODT1
/S0, /S1
/RAS
/CAS
/WE
DM0~DM7
VDD
VDDQ
V
REF
DQ
V
REF
CA
V
DD
SPD
SA0~SA2
SCL
SDA
VSS
/RESET
VTT
NC
Function
Address/Bank input
Bi-direction data bus.
Data strobes
Differential Data strobes
Clock Input. (Differential pair)
Clock Enable Input.
On-die termination control line
DIMM rank select lines.
Row address strobe
Column address strobe
Write Enable
Data masks/high data strobes
Core power supply
I/O driver power supply
I/O reference supply
Command/address reference
supply
SPD EEPROM power supply
I2C serial bus address select for
EEPROM
I2C serial bus clock for EEPROM
I2C serial bus data for EEPROM
Ground
Set DRAMs Known State
SDRAM I/O termination supply
No Connection
Features
•
RoHS compliant products.
•
JEDEC standard 1.35V(1.283V~1.45V) Power supply
•
JEDEC standard 1.5V(1.425V~1.575V) Power supply
•
VDDQ=1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
•
Clock Freq: 800MHZ for 1600Mb/s/Pin.
•
Programmable CAS Latency: 6, 7, 8, 9, 10, 11
•
Programmable Additive Latency (Posted /CAS):
0,CL-2 or CL-1 clock
•
Programmable /CAS Write Latency (CWL)
= 8(DDR3-1600)
•
8 bit pre-fetch
•
Burst Length: 4, 8
•
Bi-directional Differential Data-Strobe
•
Internal calibration through ZQ pin
•
On Die Termination with ODT pin
•
Serial presence detect with EEPROM
•
Asynchronous reset
Advantech
2
204Pin DDR3 1.5V 1600 SO-DIMM
1GB Based on 128Mx16
AQD-SD31GN16-HC
Block Diagram
1GB, 128Mx64 Module(1 Rank x16)
S0_n
RAS_n
CAS_n
WE_n
CK0_t
CK0_c
CKE0
ODT0
A[0: ]/B
N A[0:N]
CS_n
RAS_n
CAS_n
WE_n
CK_t
CK_c
CKE
ODT
A[0: ]/BA[0:N]
N
DQS0_t
DQS0_c
DM0
DQ [0:7]
DQS1_t
DQS1_c
DM1
:
DQ [8:15]
LDQS_t
LDQS_c
LDM
DQ [0:7]
UDQS_t
UDQS_c
UDM
DQ [8:15
]
240ohm
+/-1%
ZQ
SCL
SA0
SA1
SCL
Temp Sensor
A0
(with SPD)
A1
A2
EVENT_n
EVENT_n
SDA
The SPD may be
integrated with the Temp
Sensor or may be
a separate component.
D0
SCL
SA0
SA1
SCL
A0
A1
A2
(SPD)
WP
SDA
V
tt
DQS2_t
DQS2_c
DM2
DQ [16::23]
DQS3_t
DQS3_c
DM3
DQ [24::31]
LDQS_t
LDQS_c
LDM
DQ [0:7]
UDQS_t
UDQS_c
UDM
DQ [8:15]
240ohm
+/-1%
ZQ
Vtt
SPD / TS
D0-D3
D0-D3
D0-D3
D0-D3, SPD, Temp sensor
D0-D3
D0-D3
Terminated at near
card edge
V
DD
SPD
V
REF
CA
V
REF
DQ
V
DD
V
SS
CK0_t
CK0_c
CK1_t
CK1_c
ODT1
S1_n
CS_n
RAS_n
CAS_n
WE_n
CK_t
CK_c
CKE
ODT
A[0: ]/BA[0:N]
N
D1
NC
NC
NC
Temp Sensor
D0-D3
CS_n
RAS_n
CAS_n
WE_n
CK_t
CK_c
CKE
ODT
A[0: ]/BA[0:N]
N
DQS4_t
DQS4_c
DM4
DQ [32::39]
DQS5_t
DQS5_c
DM5
DQ [40::47]
LDQS_t
LDQS_c
LDM
DQ [0:7]
UDQS_t
UDQS_c
UDM
DQ [8:15]
240ohm
+/-1%
ZQ
CKE1
EVENT_n
RESET_n
D2
D0
D1
D2
D3
CS_n
RAS_n
CAS_n
WE_n
CK_t
CK_c
CKE
ODT
A[0: ]/BA[0:N]
N
DQS6_t
DQS6_c
DM6
DQ [48::55]
DQS7_t
DQS7_c
DM7
DQ [56::63]
LDQS_t
LDQS_c
LDM
DQ [0:7]
UDQS_t
UDQS_c
UDM
DQ [8:15]
240ohm
+/-1%
ZQ
Address an d Control lines
D3
NOT
ES
1. DQ wiring may differ from that shown
however ,DQ, DM, DQS_t, and DQS_c
relationships are maintained as shown
Rank 0
Vtt
Vtt
VDD
This technical information is based on industry standard data and tests believed to be reliable. However, Advantech makes no warranties, either
expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Advantech reserves the right to make changes
in specifications at any time without prior notice.
Advantech
5
Vtt
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