Hitachi Single-Chip Microcomputer
H8/3062 Series
H8/3062
HD6433062
H8/3061
HD6433061
H8/3060
HD6433060
H8/3062F-ZTAT™
HD64F3062, HD64F3062R, HD64F3062A
H8/3064F-ZTAT™
HD64F3064
Hardware Manual
ADE-602-136B
Rev. 3.0
3/20/00
Hitachi, Ltd.
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Preface
The H8/3062 Series is a series of high-performance single-chip microcontrollers that integrate
system supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include ROM, RAM, 16-bit timers, 8-bit timers, a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, a D/A converter, I/O ports, and other facilities. The two-
channel SCI supports a smart card interface handling ISO/IEC7816-3 character transmission as an
expansion function. Functions have also been added to reduce power consumption in battery-
powered applications: individual modules can be placed in standby mode, and the frequency of the
system clock supplied to the chip can be divided under program control.
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently for each area, simplifying the connection of different types of memory.
Seven MCU operating modes (modes 1 to 7) are provided, offering a choice of initial data bus
width and address space size.
With these features, the H8/3062 Series enables easy implementation of compact, high-
performance systems.
In addition to its mask ROM versions, the H8/3062 Series has F-ZTAT™* versions with on-chip
flash memory that allows programs to be rewritten after the chip is mounted on a board. This
version offers flexibility in the development of new products to meet fast-changing market needs.
This manual describes the H8/3062 Series hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
Note: * F-ZTAT™ is a trademark of Hitachi, Ltd.
List of Items Revised or Added for This Version
Page
All
Item
—
Description
H8/3064F-ZTAT and
H8/3062F-ZTAT A-Mask
Version descriptions added
Product code descriptions
amended
2
6
7
10
Table 1.1 Features
Figure 1.1 Block Diagram
Table 1.2 Comparison of H8/3062 Series Pin
Arrangements
Figure 1.4 Pin Arrangement of H8/3064F-ZTAT and
H8/3062F-ZTAT A-Mask Version(FP-100B or TFP-
100B Package, Top View)
Figure 1.5 Pin Arrangement of H8/3064F-ZTAT and
H8/3062F-ZTAT A-Mask Version(FP-100A Package,
Top View)
1.3.2
Pin Functions
Pin Functions
CPU Description amended
Notes amended
Added
Added
11
Added
12 to
15
19
20
22
Table 1.3
Description added and
revised
Notes amended
Description added
Description added
Table 1.4 Pin Assignments in Each Mode
1.4.1 Pin Arrangement
Table 1.6 Differences between H8/3062F-ZTAT,
H8/3062F-ZTAT R-Mask Version, and On-Chip Mask
ROM Versions
1.5 Notes on H8/3064F-ZTAT and H8/3062F-ZTAT
A-Mask Version
1.5.1 Pin Arrangement
1.5.3 V
CL
Pin
Figure 1.6 H8/3062F-ZTAT A-Mask Version and
H8/3064F-ZTAT
Figure 1.7 Difference between 5 V and 3 V Operation
Models
1.6 Setting Oscillation Settling Wait Time
1.7 Caution on Crystal Resonator Connection
2.1.1 Features
2.6.1 Instruction Set Overview
22
22
24, 25
24
25
26
26
27, 28
37
Added
Description revised
Description added
Description amended
Description added
Added
Description added
Description added
Total number of instructions
amended
Page
44, 45
49, 50
54
65
66
70
72
80
80, 81
132
Item
Table 2.7 Bit Manipulation Instructions
2.6.5 Notes on Use of Bit Manipulation Instructions
Table 2.13 Effective Address Calculation
Table 3.1 Operating Mode Selection
3.1.1 Operating Mode Selection
3.4.5 Mode 5
3.6.1 Comparison of H8/3062 Series Memory Maps
Figure 3.4 H8/3064F-ZTAT Memory Map in Each
Operating Mode
Figure 3.4 H8/3064F-ZTAT Memory Map in Each
Operating Mode
6.2.5 Bus Control Register(BCR)
Description
Function descriptions added
Description added
No. 1 Addressing Mode and
Instruction Format amended
Table amended
Description added
Description added
Added
Added
Addresses revised
Bit 1
Note added
136,
137
153
205 to
207
212,
213
214,
215
217 to
279
242
281 to
318
285
288
290,
291
292 to
296
298
Figure 6.3 Memory Map in 16-Mbyte Mode
Figure 6.17 Example of Wait State Insertion Timing
Table 7.21 Port A Pin Functions (Modes 1 to 7)
Table 7.23 Port B Pin Functions (Modes 1 to 5)
Table 7.24 Port B Pin Functions (Modes 6 and 7)
Section 8 16-Bit Timer
8.2.11 Timer Output Level Setting Register C (TOLR)
Section 9 8-Bit Timers
Table 9.2 8-Bit Timer Registers
9.2.3 Time Constant Registers B (TCORB)
9.2.4 Timer Control Register (8TCR)
9.2.5 Timer control/status register
Figures 9.5 and 9.7 8TCNT Access Operations
Description added
Amended
Description added
Description added
Description amended
Register names amended
Description added
Register names amended
Initial value amended
(8TCSR2)
Note added
Descriptions of bits 4 to 0
amended
Description added and
amended
Amended
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