Si5381/82 Data Sheet
Multi-DSPLL Wireless Jitter Attenuator / Clock Multiplier with
Ultra-Low Noise
The Si5381/82 is an ultra high performance wireless jitter attenuator with multiple
DSPLLs, optimized for wireless BBU (Baseband Unit) and DU (Distribution Unit) ap-
plications. The industry’s first multi-PLL wireless jitter attenuator device is capable of
replacing multiple discrete, high performance, VCXO-based jitter attenuators with a
fully integrated single chip solution. The featured multi-PLL architecture supports in-
dependent timing paths for Ethernet and CPRI (Common Public Radio Interface)
clock cleaning , and generates any low-jitter, general-purpose clocks. The fixed fre-
quency oscillator provides frequency stability for free-run and holdover modes. This
all-digital solution provides superior performance that is highly immune to external
board disturbances such as power supply noise.
Applications:
• Wireless Infrastructure
• eCPRI RRH (Remote Radio Head)
• BBU (Baseband Unit)
• DU (Distribution Unit)
• Test and Measurement
54 MHz
OSC
KEY FEATURES
• Supports simultaneous Ethernet, CPRI and
general-purpose clocking in a single device
• Input frequency range:
• Differential: 8 kHz - 750 MHz
• LVCMOS: 8 kHz to 250 MHz
• Output frequency range:
• CPRI: up to 2.94912 GHz
• Other differential: up to 735 MHz
• LVCMOS: up to 250 MHz
• Ultra-low RMS jitter:
• 72 fs typ (12 kHz–20 MHz)
• Phase noise of 122.88MHz carrier frequency:
• 118 dBc/Hz @ 100Hz offset
• ITU-T G.8262 compliant
IN_SEL
t
t
DSPLL
B
14.7456 GHz
PLL
÷INT
÷INT
÷INT
÷INT
÷INT
OUT0A
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT9A
IN0
÷INT
t
t
IN1
÷INT
IN2
÷INT
DSPLL
A
DSPLL
C
DSPLL
D
Any-Rate
PLLs
Si5382
÷INT
÷INT
÷INT
÷INT
Si5381
÷INT
÷INT
÷INT
IN3
÷INT
NVM
I
2
C/SPI
Status Flags
Control
Status
silabs.com
| Building a more connected world.
Rev. 0.95
Table of Contents
1. Features List
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Ordering Guide
3. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Frequency Configuration . . . . . . . . . . . .
3.1.1 Si5381/82 CPRI Frequency Configuration . . . . .
3.1.2 Si5381/82 Configuration for Wireless Clock Generation .
3.2 DSPLL Loop Bandwidth .
3.3 Fastlock Feature .
.
.
3.4 Modes of Operation . .
3.4.1 Initialization and Reset
3.4.2 Freerun Mode . . .
3.4.3 Lock Acquisition Mode
3.4.4 Locked Mode . . .
3.4.5 Holdover Mode . .
3.4.6 VCO Freeze Mode .
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. 6
. 6
. 7
. 8
. 8
. 8
. 9
. 9
. 9
. 9
.10
.10
.11
.12
.12
.13
.13
.13
.13
.14
.15
.15
.15
.16
.17
.19
.19
.20
.20
.21
.21
.22
.22
.22
.22
.22
.22
.22
.23
.23
3.5 External Reference (XA/XB)
3.6 Inputs (IN0, IN1, IN2, IN3) . . . . . . . .
3.6.1 Manual Input Switching (IN0, IN1, IN2, IN3) .
3.6.2 Automatic Input Selection (IN0, IN1, IN2, IN3)
3.6.3 Hitless Input Switching . . . . . . . .
3.6.4 Ramped Input Switching . . . . . . .
3.6.5 Glitchless Input Switching . . . . . . .
3.6.6 Input Configuration and Terminations . . .
3.7 Fault Monitoring . . . . . . .
3.7.1 Input LOS Detection. . . . .
3.7.2 Reference Clock LOS Detection.
3.7.3 OOF Detection . . . . . .
3.7.4 LOL Detection . . . . . . .
3.7.5 Interrupt Pin (INTRb) . . . .
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3.8 Outputs . . . . . . . . . . . . . . . . . . . .
3.8.1 Output Crosspoint . . . . . . . . . . . . . . .
3.8.2 Output Signal Format . . . . . . . . . . . . . .
3.8.3 Output Terminations. . . . . . . . . . . . . . .
3.8.4 Programmable Common Mode Voltage For Differential Outputs
3.8.5 LVCMOS Output Impedance and Drive Strength Selection. .
3.8.6 LVCMOS Output Signal Swing . . . . . . . . . . .
3.8.7 LVCMOS Output Polarity . . . . . . . . . . . . .
3.8.8 Output Enable/Disable . . . . . . . . . . . . . .
3.8.9 Output Disable During LOL . . . . . . . . . . . .
3.8.10 Output Disable During Reference LOS . . . . . . . .
3.8.11 Output Driver State When Disabled . . . . . . . . .
3.8.12 Synchronous Output Disable Feature . . . . . . . .
3.8.13 Zero Delay Mode . . . . . . . . . . . . . . .
silabs.com
| Building a more connected world.
Rev. 0.95 | 2
3.8.14 Output Divider (R) Synchronization .
3.9 Power Management .
3.11 Serial Interface
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3.10 In-Circuit Programming .
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.23
.23
.24
.24
.24
.24
3.12 Custom Factory Preprogrammed Parts .
3.13 Enabling Features and/or Configuration Settings Unavailable in ClockBuilder Pro for Factory
Preprogrammed Devices . . . . . . . . . . . . . . . . . . . . . . . .
4. Register Map
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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.26
.26
4.1 Addressing Scheme .
4.2 High-Level Register Map
5. Electrical Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . 28
40
6. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . .
7. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8. Typical Operating Characteristics
9. Pin Descriptions
10. Package Outlines
11. PCB Land Pattern
12. Top Marking
. . . . . . . . . . . . . . . . . . . . . .42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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.50
10.1 Si5381/82 9x9 mm 64-QFN Package Diagram .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13. Device Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
14. Document Change List
14.1 Revision 0.95 .
14.2 Revision 0.9 .
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. . . . . . . . . . . . . . . . . . . . . . . . . . 55
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.55
.55
silabs.com
| Building a more connected world.
Rev. 0.95 | 3
Si5381/82 Data Sheet
Features List
1. Features List
The Si5381/82 features are listed below:
• ITU-T G.8262 compliant
• Digital frequency synthesis eliminates external VCXO and ana-
log loop filter components
• DSPLL_B supports high-frequency, CPRI clocking. Remain-
ing DSPLLs support Ethernet and general-purposing clock-
ing
• Input frequency range:
• Differential: 8 kHz to 750 MHz
• LVCMOS: 8 kHz to 250 MHz
• Output frequency range:
• CPRI: up to 2.94912 GHz with JESD204B support
(DSPLL_B)
• Other differential: up to 735 MHz (DSPLL_A/C/D)
• LVCMOS: up to 250 MHz
• Ultra-low RMS jitter (12kHz - 20MHz):
• 72 fs typ at 122.88 MHz (DSPLL_B)
• 88 fs typ at 156.25 MHz (DSPLL_A/C/D)
• 79 fs typ at 322.265625 MHz (DSPLL_A/C/D)
• Typical phase noise of 122.88 MHz carrier frequency
(DSPLL_B):
• -118 dBc/Hz @ 100 Hz offset
• -133 dBc/Hz @ 1 kHz offset
• -142 dBc/Hz @ 10 kHz offset
• -149 dBc/Hz @ 100 kHz offset
• -154 dBc/Hz @ 1 MHz offset
• Highly configurable outputs compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL. CML outputs can be programmed
to have 100-1600 mVpp single-ended swing.
• Status monitoring (LOS, OOF, LOL)
• Pin controlled input switching
• Optional zero delay mode
• Hitless input clock switching: automatic or manual
• Automatic free-run and holdover modes
• Fastlock feature
• Core voltage:
• VDD: 1.8 V ±5%
• VDDA: 3.3 V ±5%
• Independent output clock supply pins: 3.3 V, 2.5 V, or 1.8 V
• Output-output skew: 75 ps max
• Serial interface: I2C or SPI
• In-circuit programmable with non-volatile OTP memory
• ClockBuilder ProTM software simplifies device configuration
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
silabs.com
| Building a more connected world.
Rev. 0.95 | 4
Si5381/82 Data Sheet
Ordering Guide
2. Ordering Guide
Table 2.1. Ordering Guide
Number of
Clock In-
puts/
Outputs
4 / 12
4 / 12
Maximum Output Frequency
CPRI Clocks
2.94912 GHz
2.94912 GHz
Other
Clocks
735 MHz
735 MHz
Package
RoHS-6,
Pb-Free
Temperature
Range
Ordering Part
Number
Si5381A-E-GM
Si5382A-E-GM
Si5381A-E-EVB
Si5382A-E-EVB
Refer-
ence
XO
XO
#
DSPLL
4
2
64-Lead
9x9 mm
QFN
Yes
–40 to +85 °C
Evaluation Board
Evaluation Board
Note:
1. Add an “R” at the end of the device to denote tape and reel options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by
ClockBuilder Pro.
Part number
format is: Si5381E-Exxxxx-GM, where “xxxxx” is a unique numerical sequence representing the pre-programmed configuration.
Figure 2.1. Ordering Part Number Fields
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Rev. 0.95 | 5
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