TS61 Series
Voltage Detector
SOT-23
Pin Definition:
1. Output
2. Ground
3. Input
General Description
The TS61 series are highly precise, low power consumption voltage detectors, manufactured using CMOS and laser
trimming technologies. Detect voltage is extremely accurate with minimal temperature drift.
Both CMOS and N-channel open drain output configurations are available.
Features
●
●
●
●
●
●
Highly Accurate:
±2%
Detecting Voltage Temperature Characteristics:
TYP
±
100ppm /°C
Low Power Consumption, 0.7uA (typ) @V
IN
=1.5V
Detect Voltage Range: 1.6V ~ 6.0V
Operating Voltage Range: 0.7V ~ 10V
Output Configuration:
N-Channel open drain or CMOS
Ordering Information
Part No.
Package
Packing
TS61CxxCX RF
SOT-23
3Kpcs / 7” Reel
TS61NxxCX RF
SOT-23
3Kpcs / 7” Reel
Note:
* Where
xx
denotes voltage option, available are
20=
2.0V
23=
2.3V
24=
2.4V
25=
2.5V
27=
2.7V
30=
3.0V
33=
3.3V
40=
4.0V
42=
4.2V
44=
4.4V
45=
4.5V
Contact factory for additional voltage option.
* TS61C: CMOS output
* TS61N: N-Channel Open Drain Output
Applications
●
●
●
●
●
●
Battery-operated systems
Microprocessor reset circuitry
Memory battery back-up circuits
Power-on reset circuits
Power failure detection
System battery life and charge voltage monitors
Block Diagram
CMOS Output
N-Channel Open Drain Output
1/7
Version: A07
TS61 Series
Voltage Detector
Absolute Maximum Rating
Parameter
Input Voltage
Output Current
Output Voltage
Power Dissipation
CMOS
N-channel open drain
SOT-23
Symbol
V
IN
Io
V
OUT
P
D
T
A
Maximum
+12
50
(Gnd – 0.3) to (V
IN
+ 0.3)
(Gnd – 0.3) to 12
150
-40 ~ +85
Unit
V
mA
V
mW
o
o
Operating Ambient Temperature Range
C
Storage Temperature
T
STG
-65 ~ +150
C
Note: Stress above those listed under absolute maximum ratings may cause permanent damage to the device. These
are stress ratings only and functional operation of the device at these or any other conditions above those
indicated in the operation section of the specifications is not implied.
Electrical Specifications
(Ta = 25
o
C, unless otherwise noted)
Parameter
Detect Voltage
Hysteresis range
V
IN
=1.5V
V
IN
=2.0V
Supply Current
V
IN
=3.0V
V
IN
=4.0V
V
IN
=5.0V
Operating Voltage
V
DF
(T)=1.6V~6V
N-channel V
DS
=5V
V
IN
=1.0V
V
IN
=2.0V
Output Current
V
IN
=3.0V
V
IN
=4.0V
V
IN
=5.0V
P-channel V
DS
=2.1V (with CMOS output)
V
IN
=8.0V
Temperature
Characteristics
-40°C
≤
T
A
≤
85°C
I
OUT
ΔV
DF
ΔT
A
xV
DF
--
--
-10.0
±100
-2.0
--
mA
ppm /
°C
ms
4
--
5
I
OUT
1.0
3.0
5.0
6.0
7.0
2.2
7.7
10.1
11.5
13.0
--
--
--
--
--
mA
3
V
IN
Iss
Conditions
Symbol
V
DF
V
HYS
/ V
DF
Min
V
DF
x 0.98
2
--
--
--
--
--
0.7
Typ
V
DF
--
0.7
0.8
0.9
1.0
1.1
--
Max
V
DF
x 1.02
8
2.3
2.7
3.0
3.2
3.6
10.0
Unit
V
%
Circuit
1
1
µA
2
V
1
Delay Time
Vdr
V
OUT
inversion
t
DLY
--
--
0.2
Note: V
DF
(T): Established Detect Voltage Value, 1.6V ~ 6.0V
±2%
for Standard Voltage Detectors
Release Voltage: V
DR
= V
DF
+ V
HYS
2/7
Version: A07
TS61 Series
Voltage Detector
Typical Application Circuit
CMOS Output
N-Channel Open Drain Output
Measuring Circuit
Test Circuit 1
Test Circuit 2
Test Circuit 3
* Not Necessary with CMOS output
product
Test Circuit 4
Test Circuit 5
* Not Necessary with CMOS output products
3/7
Version: A07
TS61 Series
Voltage Detector
Directions for use
1. Please use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or
permanent damage to the device.
2. When a resistor is connected between the V
IN
pin and the input CMOS output configurations, oscillation may occur
as a result of voltage drops at R
IN
if load current (I
OUT
) exists. (refer to the Oscillation Description
①
below).
3. When a resisted is connected between the V
IN
pin and the input with CMOS output configurations, irrespective of
N-ch output configurations, oscillation may occur as a result of through current at the time of voltage release even if
load current (I
OUT
) does not exist. (refer to the Oscillation Description
②
below)
4. In order to stabilize the IC’s operations, please ensure that V
IN
pin’s input frequency’s rise and fall times are more
than several
µs/V.
5. Please use N-ch open drains configuration, when a resistor R
IN
is connected between the V
IN
pin and power source.
In such cases, please ensure that R
IN
is less than kΩ and that C is more than 0.1µF.
Diagram: Circuit using an input resistor
Oscillation Description
OUTPUT CURRENT OSCILLATION WITH THE CMOS OUTPUT CONFIGURATION
When the voltage applied at IN rises, release operations commence and the detector’s output voltage increases. Load
current (I
OUT
) will flow at R
L
. Because a voltage drop (R
IN
x I
OUT
) is produced at the R
IN
resistor, located between the
input (IN) and the V
IN
pin, the load current will flow via the IC’s V
IN
pin. The voltage drop will also lead to a fall in the
voltage level at the V
IN
pin. When the V
IN
pin voltage level falls below the detec voltage level, detect operations will
commence. Following detect operations, load current flow will cease and since voltage drop at R
IN
will disappear, the
voltage level at the V
IN
pin will rise and release operations will begin over again. Oscillation may occur with this
“release-detect-release” repetition. Further, this condition will also appear via means of a similar mechanism during
detect operations.
Diagram 1: Oscillation in relation to output current
4/7
Version: A07
TS61 Series
Voltage Detector
Oscillation Description (Continue)
OUTPUT CURRENT OSCILLATION WITH THE CMOS OUTPUT CONFIGURATION
Since the TS61 series are CMOS ICs, through current will flow when the IC’s internal circuit switching operates (during
release and detect operations). Consequently, oscillation is liable to occur as a result of drops in voltage at the through
current’s resistor (R
IN
) during release voltage operations (refer to diagram 2). Since hysteresis exists during detect
operation, oscillation is unlikely to occur.
Diagram 2: Oscillation in relation to through current
Function Description
1. When input voltage (V
IN
) rises above detect voltage (V
DF
), output voltage (V
OUT
) will be equal to V
IN
. (A condition of
high impedance exists with N-ch open drain output configurations).
2. When input voltage (V
IN
) falls below detect voltage (V
DF
), output voltage will be equal to the ground voltage (V
SS
).
3. When input voltage (V
IN
) falls to a level below that of the minimum operating voltage (V
MIN
), output will become
unstable. In this condition, V
IN
will equal the pulled-up output (should output be pull-up).
4. When input voltage (V
IN
) rises above the ground voltage (V
SS
) level, output will be unstable at levels below the
minimum operating voltage (V
MIN
). Between the V
MIN
and detect release voltage V
DR
level, the ground voltage (V
SS
)
level will be maintained.
5. When input voltage (V
IN
) rises above detect release voltage (V
DR
), output voltage (V
OUT
) will be equal to V
IN
. (A
condition of high impedance exists with N-ch open drain output configurations.)
6. The difference between V
DR
and V
DF
represents the hysteresis range.
Timing Chart
5/7
Version: A07
stm32/stm8
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