74F169 4-Stage Synchronous Bidirectional Counter
April 1988
Revised September 2000
74F169
4-Stage Synchronous Bidirectional Counter
General Description
The 74F169 is a fully synchronous 4-stage up/down
counter. The 74F169 is a modulo-16 binary counter. Fea-
tures a preset capability for programmable operation, carry
lookahead for easy cascading and a U/D input to control
the direction of counting. All state changes, whether in
counting or parallel loading, are initiated by the
LOW-to-HIGH transition of the clock.
Features
s
Asynchronous counting and loading
s
Built-in lookahead carry capability
s
Presettable for programmable operation
Ordering Code:
Order Number
74F169SC
74F169SJ
74F169PC
Package Number
M16A
M16D
N16E
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009488
www.fairchildsemi.com
74F169
Unit Loading/Fan Out
Pin Names
CEP
CET
CP
P
0
–P
3
PE
U/D
Q
0
–Q
3
TC
Description
Count Enable Parallel Input (Active LOW)
Count Enable Trickle Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Parallel Enable Input (Active LOW)
Up-Down Count Control Input
Flip-Flop Outputs
Terminal Count Output (Active LOW)
U.L.
HIGH/LOW
1.0/1.0
1.0/2.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
20
µ
A/
−
1.2 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
−
1 mA/20 mA
−
1 mA/20 mA
Functional Description
The 74F169 uses edge-triggered J-K type flip-flops and
has no constraints on changing the control or data input
signals in either state of the clock. The only requirement is
that the various inputs attain the desired state at least a
setup time before the rising edge of the clock and remain
valid for the recommended hold time thereafter. The paral-
lel load operation takes precedence over other operations,
as indicated in the Mode Select Table. When PE is LOW,
the data on the P
0
–P
3
inputs enters the flip-flops on the
next rising edge of the clock. In order for counting to occur,
both CEP and CET must be LOW and PE must be HIGH;
the U/D input then determines the direction of counting.
The Terminal Count (TC) output is normally HIGH and goes
LOW, provided that CET is LOW, when a counter reaches
zero in the Count Down mode or reaches 15 for the
74F169 in the Count Up mode. The TC output state is not a
function of the Count Enable Parallel (CEP) input level.
Since the TC signal is derived by decoding the flip-flop
states, there exists the possibility of decoding spikes on
TC. For this reason the use of TC as a clock signal is not
recommended (see logic equations below).
1. Count Enable
=
CEP • CET • PE
2. Up: (74F169): TC
=
Q
0
• Q
1
• Q
2
• Q
3
• (Up) • CET
3. Down: TC
=
Q
0
• Q
1
• Q
2
• Q
3
• (Down) • CET
Mode Select Table
PE
L
H
H
H
H
CEP CET U/D
X
L
L
H
X
X
L
L
X
H
X
H
L
X
X
Action on Rising
Clock Edge
Load (P
n
→
Q
n
)
Count Up (Increment)
Count Down (Decrement)
No Change (Hold)
No Change (Hold)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
State Diagram
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2
74F169
Logic Diagram
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74F169
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
I
IL
I
OS
I
CCL
Input LOW Current
Output Short-Circuit Current
Power Supply Current
−60
35
4.75
3.75
−0.6
−1.2
−150
52
10% V
CC
5% V
CC
10% V
CC
2.5
2.7
0.5
5.0
7.0
50
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
V
V
µA
µA
µA
V
µA
Min
Min
Min
Max
Max
Max
0.0
0.0
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −1
mA
I
OL
=
20 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V (except CET)
V
IN
=
0.5V (CET)
V
OUT
=
0V
V
O
=
LOW
mA
mA
mA
Max
Max
Max
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4
74F169
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Maximum Count Frequency
Propagation Delay
CP to Q
n
(PE HIGH or LOW)
Propagation Delay
CP to TC
Propagation Delay
CET to TC
Propagation Delay
U/D to TC
90
3.0
4.0
5.5
4.0
2.5
2.5
3.5
4.0
6.5
9.0
12.0
8.5
4.5
8.5
8.5
8.0
8.5
11.5
15.5
12.5
6.5
11.0
11.5
12.0
V
CC
= +5.0V
C
L
=
50 pF
Typ
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
C
L
=
50 pF
Min
60
3.0
4.0
5.5
4.0
2.5
2.5
3.5
4.0
12.0
16.0
20.0
15.0
9.0
12.0
16.0
14.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
70
3.0
4.0
5.5
4.0
2.5
2.5
3.5
4.0
9.5
13.0
17.5
13.0
7.0
12.0
12.5
13.0
Max
MHz
ns
ns
ns
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
Setup Time, HIGH or LOW
P
n
to CP
Hold Time, HIGH or LOW
P
n
to CP
Setup Time, HIGH or LOW
CEP or CET to CP
Hold Time, HIGH or LOW
CEP or CET to CP
Setup Time, HIGH or LOW
PE to CP
Hold Time, HIGH or LOW
PE to CP
Setup Time, HIGH or LOW
U/D to CP
Hold Time, HIGH or LOW
U/D to CP
CP Pulse Width
HIGH or LOW
4.0
4.0
3.0
3.0
7.0
5.0
0
0.5
8.0
8.0
1.0
0
11.0
7.0
0
0
4.0
7.0
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
Min
4.5
4.5
3.5
3.5
8.0
8.0
0
1.0
10.0
10.0
1.0
0
14.0
12.0
0
0
6.0
9.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
4.5
4.5
3.5
3.5
8.0
6.5
0
0.5
9.0
9.0
1.0
0
12.5
8.5
0
0
4.5
8.0
ns
ns
ns
ns
ns
Max
Units
5
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