74ACT534 Octal D-Type Flip-Flop with 3-STATE Outputs
November 1988
Revised November 1999
74ACT534
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACT534 is a high-speed, low-power octal D-type flip-
flop featuring separate D-type inputs for each flip-flop and
3-STATE outputs for bus-oriented applications. A buffered
Clock (CP) and Output Enable (OE) are common to all flip-
flops. The ACT534 is the same as the ACT374 except that
the outputs are inverted.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Edge-triggered D-type inputs
s
Buffered positive edge-triggered clock
s
3-STATE outputs for bus-oriented applications
s
Outputs source/sink 24 mA
s
ACT534 has TTL-compatible inputs
s
Inverted output version of ACT374
Ordering Code:
Order Number
74ACT534SC
74ACT534SJ
74ACT534PC
Package Number
M20B
M20D
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
–D
7
CP
OE
O
0
–O
7
Data Inputs
Clock Pulse Input
3-STATE Output Enable Input
Complementary 3-STATE Outputs
Description
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009965
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74ACT534
Functional Description
The ACT534 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE complementary out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and
hold times requirements on the LOW-to-HIGH Clock (CP)
transition. With the Output Enable (OE) LOW, the contents
of the eight flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops.
Function Table
Inputs
CP
Output
D
H
L
X
X
O
L
H
O
0
Z
L
X
OE
L
L
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
Z
=
High Impedance
O
0
=
Value stored from previous clock cycle
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74ACT534
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
PDIP
140°C
±50
mA
−65°C
to
+150°C
±50
mA
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−0.5V
to
+7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (∆V/∆t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Maximum 3-STATE
Current
Maximum
I
CC
/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
5.5
5.5
4.0
0.6
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.1
±0.25
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
±2.5
1.5
75
−75
40.0
µA
µA
mA
mA
mA
µA
V
V
V
V
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24
mA
I
OH
= −24
mA (Note 2)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 2)
V
I
=
V
CC
, GND
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
−
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Units
Conditions
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
3
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74ACT534
AC Electrical Characteristics
V
CC
Symbol
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Maximum Clock
Frequency
Propagation Delay
CP to Q
n
Propagation Delay
CP to Q
n
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
(V)
(Note 4)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
2.5
2.0
2.5
2.0
1.5
1.5
Min
T
A
= +25°C
C
L
=
50 pF
Typ
100
6.5
6.0
6.5
6.0
7.0
5.5
11.5
10.5
12.0
11.0
12.5
10.5
Max
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
120
2.0
2.0
2.0
2.0
1.0
1.0
12.5
12.0
12.5
11.5
13.5
10.5
Max
MHz
ns
ns
ns
ns
ns
ns
Units
Note 4:
Voltage Range 5.0 is 5.0V
±
0.5V
AC Operating Requirements
V
CC
Symbol
t
S
t
H
t
W
Parameter
Setup Time, HIGH or LOW
D
n
to CP
Hold Time, HIGH or LOW
D
n
to CP
CP Pulse Width
HIGH or LOW
Note 5:
Voltage Range 5.0 is 5.0V
±
0.5V
T
A
= +25°C
C
L
=
50 pF
Typ
1.0
−1.0
2.0
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Guaranteed Minimum
Units
(V)
(Note 5)
5.0
5.0
5.0
3.5
1.0
3.5
4.0
1.5
3.5
ns
ns
ns
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
40.0
Units
pF
pF
V
CC
=
OPEN
V
CC
=
5.0V
Conditions
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4
74ACT534
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
Package Number M20B
5
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